DLPS119B December   2018  – May 2022 DLP2010NIR

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
      1. 6.13.1 Software Requirements
    14. 6.14 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FQJ|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Absolute Maximum Ratings

(see (1))
MIN MAX UNIT
Supply voltage VDD Supply voltage for LVCMOS core logic and LPSDR low speed interface(2)
–0.5 2.3 V
VDDI Supply voltage for SubLVDS receivers(2) –0.5 2.3 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode(2) (3) –0.5 10.6 V
VBIAS Supply voltage for micromirror electrode bias circuits (2) –0.5 19 V
VRESET Supply voltage for micromirror electrode reset circuit (2) –15 0.3 V
|VDDI–VDD| Supply voltage delta (absolute value)(4) 0.3 V
|VBIAS–VOFFSET| Supply voltage delta (absolute value)(5) 11 V
|VBIAS–VRESET| Supply voltage delta (absolute value)(6) 34 V
Input voltage Input voltage for other inputs LPSDR(2) –0.5 VDD + 0.5 V
Input voltage for other inputs SubLVDS(2) (7) –0.5 VDDI + 0.5 V
Input pins |VID| SubLVDS input differential voltage (absolute value)(7) 810 mV
IID SubLVDS input differential current 8.1 mA
Clock frequency ƒclock Clock frequency for low speed interface LS_CLK 130 MHz
ƒclock Clock frequency for high speed interface DCLK 620 MHz
Environmental TARRAY and TWINDOW Temperature – operational (8) –20 90 °C
Temperature – non-operational (8) –40 90 °C
TDP Dew point (operating and non-operating) 81 °C
|TDELTA| Absolute Temperature delta between any point on the window edge and the ceramic test point TP1 (9) 30 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.
(3) VOFFSET supply transients must fall within specified voltages.
(4) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(6) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.
(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(8) The highest temperature of the active array (as calculated by the Section 7.6), or of any point along the Window Edge as defined in href="Micromirror-Array-Temperature-Calculation-DLPS0008740.dita#DLPS0008740/DLPS0001803"/>. The locations of thermal test points TP2 and TP3 in href="Micromirror-Array-Temperature-Calculation-DLPS0008740.dita#DLPS0008740/DLPS0001803"/> are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that test point should be used.
(9) Temperature delta is the highest difference from the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure 19. The window test points TP2 and TP3 shown in Figure 19 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.