DLPS207B February 2022 – December 2023 DLP2021-Q1
PRODUCTION DATA
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
DATA(0) | A2 | LVCMOS input | Data bus. Synchronous to rising edge and falling edge of DCLK |
DATA(1) | A4 | ||
DATA(2) | B2 | ||
DATA(3) | B3 | ||
DATA(4) | B5 | ||
DATA(5) | C2 | ||
DATA(6) | C3 | ||
DATA(7) | B4 | ||
DATA(8) | C5 | ||
DATA(9) | D2 | ||
DCLK | F4 | Data clock | |
LOADB | F3 | Parallel latch load enable. Synchronous to rising edge and falling edge of DCLK | |
SCTRL | E4 | Serial control (sync). Synchronous to rising edge and falling edge of DCLK | |
TRC | F2 | Toggle rate control. Synchronous to rising edge and falling edge of DCLK | |
DAD_BUS | B15 | Reset control serial bus. Synchronous to rising edge of SAC_CLK | |
RESET_OEZ | C15 | Active low. Output enable signal for internal reset driver circuitry | |
RESET_STROBE | B13 | Rising edge on RESET_STROBE latches in the control signals | |
SAC_BUS | A15 | Stepped address control serial bus. Synchronous to rising edge of SAC_CLK | |
SAC_CLK | A14 | Stepped address control clock | |
TEMP_MINUS | G13 | Analog input | Calibrated temperature diode used to assist accurate temperature measurements of DMD die |
TEMP_PLUS | G2 | ||
VBIAS | D15 | Power | Power supply for positive bias level of mirror reset signal |
VCC | A5, B12, C14, D12, F13, G3 | Power supply for low voltage CMOS logic. Power supply for normal high voltage at mirror address electrodes. Power supply for offset level of mirror reset signal during power down | |
VOFFSET | E14 | Power supply for high voltage CMOS logic. Power supply for stepped high voltage at mirror address electrodes. Power supply for offset level of mirror reset signal | |
VRESET | D14 | Power supply for negative reset level of mirror reset signal | |
VSS | A3, A13, B14, C4, C12, C13, D13, E3, E5, E12, F12, F14, G4, G12 | Common return for all power | |
RESERVED | A1, A12, A16,B1, B16, D3, D4, D5, E2, E13,E15, F1, F5, F15, F16, G1, G5, G14, G15, G16 | Reserved | Do not connect. |