DLPS207B February   2022  – December 2023 DLP2021-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (cont.)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.     12
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Timing Requirements
    9.     16
    10. 6.8  System Mounting Interface Loads
    11.     18
    12. 6.9  Micromirror Array Physical Characteristics
    13.     20
    14.     21
    15. 6.10 Micromirror Array Optical Characteristics
    16. 6.11 Window Characteristics
    17. 6.12 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Micromirror Array
      2. 7.3.2 Double Data Rate (DDR) Interface
      3. 7.3.3 Micromirror Switching Control
      4. 7.3.4 DMD Voltage Supplies
      5. 7.3.5 Logic Reset
      6. 7.3.6 Temperature Sensing Diode
        1. 7.3.6.1 Temperature Sense Diode Theory
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill and Alignment
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Application Mission Profile Consideration
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequencing Requirements
      1. 9.1.1 Power Up and Power Down
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Temperature Diode Pins
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Device Handling
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT
IDD Supply current: VDD VDD = 1.95 V 30 mA
IOFFSET Supply current: VOFFSET VOFFSET = 8.75 V 15 mA
IBIAS Supply current: VBIAS VBIAS = 16.5 V 2.3 mA
IRESET Supply current: VRESET VRESET = –10.5 V 3.3 mA
POWER
PDD Supply power dissipation: VDD VDD = 1.95 V 60 mW
POFFSET Supply power dissipation: VOFFSET VOFFSET = 8.75 V 132 mW
PBIAS Supply power dissipation: VBIAS VBIAS = 16.5 V 38 mW
PRESET Supply power dissipation: VRESET VRESET = –10.5 V 30 mW
PTOTAL Supply power dissipation: Total 260 mW
LVCMOS Buffers
VOH High level output voltage IOH = –2 mA 0.8 × VDD V
VOL Low level output voltage IOH = 2 mA 0.2 × VDD V
IIL Low level input current(2) VDD = 1.95 V; VI = 0 V –100 nA
IIH High level output current(2) VDD = 1.95 V; VI = 1.95 V 135 uA
IIL2 Low level input current(3) VDD = 0.0 V –5 uA
IIH2 High level output current(3) VDD = 1.95 V 785 uA
CAPACITANCE
CIN Input capacitance ƒ = 1 MHz 10 pF
COUT Output capacitance ƒ = 1 MHz 15 pF
CTEMP Temperature sense diode capacitance ƒ = 1 MHz 25 pF
(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
(2) Specification is for LVCMOS input pins which do not have pull up or pull down resistors.
(3) Specification is for LVCMOS input pins which do have pull down resistors.