DLPS207B February   2022  – December 2023 DLP2021-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (cont.)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.     12
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Timing Requirements
    9.     16
    10. 6.8  System Mounting Interface Loads
    11.     18
    12. 6.9  Micromirror Array Physical Characteristics
    13.     20
    14.     21
    15. 6.10 Micromirror Array Optical Characteristics
    16. 6.11 Window Characteristics
    17. 6.12 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Micromirror Array
      2. 7.3.2 Double Data Rate (DDR) Interface
      3. 7.3.3 Micromirror Switching Control
      4. 7.3.4 DMD Voltage Supplies
      5. 7.3.5 Logic Reset
      6. 7.3.6 Temperature Sensing Diode
        1. 7.3.6.1 Temperature Sense Diode Theory
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill and Alignment
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Application Mission Profile Consideration
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequencing Requirements
      1. 9.1.1 Power Up and Power Down
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Temperature Diode Pins
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Device Handling
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
SUPPLY VOLTAGE RANGE
VDD Supply voltage for LVCMOS core logic
Supply voltage for LPSDR low-speed interface		 1.7 1.8 1.95 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode 8.25 8.5 8.75 V
VBIAS Supply voltage for mirror electrode 15.5 16 16.5 V
VRESET Supply voltage for micromirror electrode –9.5 –10 –10.5 V
| VBIAS–VOFFSET | Supply voltage delta (absolute value) 8.75 V
| VBIAS–VFRESET | Supply voltage delta (absolute value) 28 V
LVCMOS Buffers
VIH Positive going threshold voltage 0.7 VDD+0.3 x VDD
VIL Negative going threshold voltage –0.3 0.3  x VDD
CLOCK FREQUENCY
ƒmax Clock frequency for high speed interface SAC_CLK 20 76.2 80 MHz
DCDIN Duty Cycle Distortion tolerance SAC_CLK 30% 70%
ƒmax Clock frequency for high speed interface DCLK 20 76.2 80 MHz
DCDIN Duty Cycle Distortion tolerance DCLK 30% 70%
TEMPERATURE DIODE
ITEMP_DIODE Max current source into temperature diode 120 μA
ENVIRONMENTAL
TARRAY Operating DMD array temperature(3) –40 105 °C
ILLUV Illumination, wavelength < 395 nm (2) 2 mW/cm 2
ILLOVERFILL Illumination overfill maximum heat load in area shown in Illumination Overfill Diagram 40 mW/mm 2