DLPS144F july 2018 – july 2023 DLP230NP
PRODUCTION DATA
PIN(1) | TYPE | SIGNAL | DATA RATE | DESCRIPTION | PACKAGE NET LENGTH(2) (mm) | |
---|---|---|---|---|---|---|
NAME | NO. | |||||
DATA INPUTS | ||||||
D_N(0) | A2 | I | SubLVDS | Double | Data, negative | 1.96 |
D_N(1) | A1 | I | SubLVDS | Double | Data, negative | 1.42 |
D_N(2) | C1 | I | SubLVDS | Double | Data, negative | 1.35 |
D_N(3) | B4 | I | SubLVDS | Double | Data, negative | 3.36 |
D_N(4) | F5 | I | SubLVDS | Double | Data, negative | 4.29 |
D_N(5) | D4 | I | SubLVDS | Double | Data, negative | 3.20 |
D_N(6) | E1 | I | SubLVDS | Double | Data, negative | 1.76 |
D_N(7) | F3 | I | SubLVDS | Double | Data, negative | 2.66 |
D_P(0) | A3 | I | SubLVDS | Double | Data, positive | 1.97 |
D_P(1) | B1 | I | SubLVDS | Double | Data, positive | 1.49 |
D_P(2) | C2 | I | SubLVDS | Double | Data, positive | 1.44 |
D_P(3) | A4 | I | SubLVDS | Double | Data, positive | 3.45 |
D_P(4) | E5 | I | SubLVDS | Double | Data, positive | 4.32 |
D_P(5) | D5 | I | SubLVDS | Double | Data, positive | 3.27 |
D_P(6) | E2 | I | SubLVDS | Double | Data, positive | 1.85 |
D_P(7) | F2 | I | SubLVDS | Double | Data, positive | 2.75 |
DCLK_N | C3 | I | SubLVDS | Double | Clock, negative | 1.94 |
DCLK_P | D3 | I | SubLVDS | Double | Clock, positive | 2.02 |
CONTROL INPUTS | ||||||
LS_WDATA | A12 | I | LPSDR(1) | Single | Write data for low speed interface | 2.16 |
LS_CLK | B12 | I | LPSDR | Single | Clock for low-speed interface | 3.38 |
DMD_DEN_ARSTZ | B14 | I | LPSDR | Single | Asynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. | 0.67 |
DMD_DEN_ARSTZ | F1 | I | LPSDR | Single | 14.90 | |
LS_RDATA | C13 | O | LPSDR | Single | Read data for low-speed interface | 2.44 |
POWER | ||||||
VBIAS(3) | A15 | Power | Supply voltage for positive bias level at micromirrors | |||
VBIAS(3) | A5 | Power | ||||
VOFFSET(3) | F13 | Power | Supply
voltage for HVCMOS core logic. Supply voltage for stepped high level
at micromirror address electrodes. Supply voltage for offset level at micromirrors |
|||
VOFFSET(3) | F4 | Power | ||||
VRESET | B15 | Power | Supply voltage for negative reset level at micromirrors | |||
VRESET | B5 | Power | ||||
VDD(3) | C15 | Power | Supply voltage for LVCMOS core logic. Supply voltage for LPSDR
inputs. Supply voltage for normal high level at micromirror address electrodes |
|||
VDD | C5 | Power | ||||
VDD | D14 | Power | ||||
VDD | D15 | Power | ||||
VDD | E14 | Power | ||||
VDD | E15 | Power | ||||
VDD | F14 | Power | ||||
VDD | F15 | Power | ||||
VDDI | C14 | Power | Supply voltage for SubLVDS receivers | |||
VDDI | C4 | Power | ||||
VDDI | D13 | Power | ||||
VDDI | E13 | Power | ||||
VSS | A13 | Ground | Common return. Ground for all power |
|||
VSS | A14 | Ground | ||||
VSS | B13 | Ground | ||||
VSS | B2 | Ground | ||||
VSS | B3 | Ground | ||||
VSS | C12 | Ground | ||||
VSS | D1 | Ground | ||||
VSS | D12 | Ground | ||||
VSS | D2 | Ground | ||||
VSS | E12 | Ground | ||||
VSS | E3 | Ground | ||||
VSS | E4 | Ground | ||||
VSS | F12 | Ground |
NUMBER | SYSTEM BOARD | ||
---|---|---|---|
A6 | Do not connect. | ||
A7 | Do not connect. | ||
A8 | Do not connect. | ||
A9 | Do not connect. | ||
A10 | Do not connect. | ||
A11 | Do not connect. | ||
F6 | Do not connect. | ||
F7 | Do not connect. | ||
F8 | Do not connect. | ||
F9 | Do not connect. | ||
F10 | Do not connect. | ||
F11 | Do not connect. |