DLPS247 August   2024 DLP472TP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     12
    6. 5.5  Thermal Information
    7. 5.6  Electrical Characteristics
    8. 5.7  Switching Characteristics
    9. 5.8  Timing Requirements
    10.     17
    11. 5.9  System Mounting Interface Loads
    12.     19
    13. 5.10 Micromirror Array Physical Characteristics
    14.     21
    15. 5.11 Micromirror Array Optical Characteristics
    16.     23
    17. 5.12 Window Characteristics
    18. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 LPSDR Low-Speed Interface
      3. 6.3.3 High-Speed Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 Timing Requirements

Over operating free-air temperature range (unless otherwise noted) (1)
MIN NOM MAX UNIT
LPSDR
tf Fall slew rate (2) (80% to 20%) × VDD(5) 0.25 V/ns
tc Cycle time LS_CLK(5) 50% to 50% reference points(5) 7.7 8.3 ns
tr Rise slew rate (1) (30% to 80%) × VDD(6) 1 3 V/ns
tf Fall slew rate (1) (70% to 20%) x VDD(6) 1 3 V/ns
tr Rise slew rate (2) (20% to 80%) × VDD(6) 0.25 V/ns
tW(H) Pulse duration LS_CLK high 50% to 50% reference points(5) 3.1 ns
tW(L) Pulse duration LS_CLK low 50% to 50% reference points(5) 3.1 ns
tWINDOW Window time(1)(3) Setup time + Hold time(5) 3 ns
tDERATING Window time derating(1)(3) For each 0.25 V/ns reduction in slew rate below 1 V/ns(8) 0.35 ns
tsu Setup time LS_WDATA valid before LS_CLK(5) 1.5 ns
th Hold time LS_WDATA valid after LS_CLK(5) 1.5 ns
SubLVDS
tr Rise slew rate 20% to 80% reference points(7) 0.7 1 V/ns
tf Fall slew rate 80% to 20% reference points(7) 0.7 1 V/ns
tc Cycle time D_CLK(9) 50% to 50% reference points(9) 1.35 1.39 ns
tW(H) Pulse duration DCLK high 50% to 50% reference points(9) 0.7 ns
tW(L) Pulse duration DCLK low 50% to 50% reference points(9) 0.7 ns
tsu Setup time DATA valid before D_CLK(9) 0.17 ns
th Hold time DATA valid after D_CLK(9) 0.17 ns
tWINDOW Window time Setup time + Hold time(9)(10) 0.25 ns
tPOWER Power-up receiver(4) 200 ns
(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise and fall slew rate in Figure 6-3
(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-3
(3) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.
(4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
(5) See Figure 6-2 .
(6) See Figure 6-3 .
(7) See Figure 6-4.
(8) See Figure 6-5.
(9) See Figure 6-6.
(10) See Figure 6-7.