DLPS160B April   2019  – February 2023 DLP480RE

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 DMD Die Temperature Sensing
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
      1.      Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.
MIN NOM MAX UNIT
VOLTAGE SUPPLY
VCC LVCMOS logic supply voltage#DLPS1609720 1.65 1.8 1.95 V
VOFFSET Mirror electrode and HVCMOS voltage#DLPS1609720#DLPS1603066 9.5 10 10.5 V
VBIAS Mirror electrode voltage#DLPS1609720 17.5 18 18.5 V
VRESET Mirror electrode voltage#DLPS1609720 –14.5 –14 –13.5 V
|VBIAS – VOFFSET| Supply voltage difference (absolute value)#DLPS1607978 10.5 V
|VBIAS – VRESET| Supply voltage difference (absolute value)#DLPS1607936 33 V
LVCMOS INTERFACE
VIH(DC) DC input high voltage#DLPS1605892 0.7 × VCC VCC + 0.3 V
VIL(DC) DC input low voltage#DLPS1605892 –0.3 0.3 × VCC V
VIH(AC) AC input high voltage#DLPS1605892 0.8 × VCC VCC + 0.3 V
VIL(AC) AC input low voltage#DLPS1605892 –0.3 0.2 × VCC V
tPWRDNZ PWRDNZ pulse duration#DLPS1605746 10 ns
SCP INTERFACE
ƒSCPCLK SCP clock frequency#DLPS160808 500 kHz
tSCP_PD Propagation delay, Clock to Q, from rising–edge of SCPCLK to valid SCPDO#DLPS1609761 0 900 ns
tSCP_NEG_ENZ Time between falling-edge of SCPENZ and the first rising- edge of SCPCLK 1 µs
tSCP_POS_ENZ Time between falling-edge of SCPCLK and the rising-edge of SCPENZ 1 µs
tSCP_DS SCPDI Clock setup time (before SCPCLK falling edge)#DLPS1609761 800 ns
tSCP_DH SCPDI Hold time (after SCPCLK falling edge)#DLPS1609761 900 ns
tSCP_PW_ENZ SCPENZ inactive pulse duration (high level) 2 µs
LVDS INTERFACE
ƒCLOCK Clock frequency for LVDS interface (all channels), DCLK#DLPS1605806 400 MHz
|VID| Input differential voltage (absolute value)#DLPS160398 150 300 440 mV
VCM Common mode voltage#DLPS160398 1100 1200 1300 mV
VLVDS LVDS voltage#DLPS160398 880 1520 mV
tLVDS_RSTZ Time required for LVDS receivers to recover from PWRDNZ 2000 ns
ZIN Internal differential termination resistance 80 100 120 Ω
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
ENVIRONMENTAL
TARRAY Array temperature, Long–term operational#DLPS1604684#DLPS1603629#DLPS1603159#DLPS1609678 10 40 to 70#DLPS1603159 °C
Array temperature, Short–term operational#DLPS1603629#DLPS1605797 0 10 °C
TWINDOW Window temperature – operational#T4852280-16#T4852280-14 85 °C
|TDELTA| Absolute temperature difference between any point on the window edge and the ceramic test point TP1#DLPS1604914 #DLPS1605061 14 °C
TDP -AVG Average dew point temperature (non–condensing)#DLPS1605716 28 °C
TDP-ELR Elevated dew point temperature range (non-condensing)#DLPS1603111 28 36 °C
CTELR Cumulative time in elevated dew point temperature range 24 Months
ILLUMINATION (Lamp)
L Operating system luminance#DLPS1605061 4000 lm
ILLUV Illumination Wavelengths < 395 nm#DLPS1604684 0.68 2.00 mW/cm2
ILLVIS Illumination Wavelengths between 395 nm and 800 nm Thermally limited mW/cm2
ILLIR Illumination Wavelengths > 800 nm 10 mW/cm2
ILLθ Illumination Marginal Ray Angle#T4852280-14 55 deg
ILLUMINATION (Solid State)
L Operating system luminance#DLPS1605061

6000

 lm
ILLUV Illumination Wavelengths < 436 nm#DLPS1604684

0.45

 mW/cm2
ILLVIS Illumination Wavelengths between 436 nm and 800 nm Thermally limited mW/cm2
ILLIR Illumination Wavelengths > 800 nm

10

 mW/cm2
ILLθ Illumination Marginal Ray Angle#T4852280-14

55

lm
(1) All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified max voltages.
(3) To prevent excess current, the supply voltage difference |VBIAS – VOFFSET| must be less than specified limit. See GUID-3148EEF2-489E-4025-AD64-40594FE0958A.html#GUID-3148EEF2-489E-4025-AD64-40594FE0958A, GUID-E03635F4-9EAC-4BD0-97AE-23AFBE0EC956.html#DLPS1609748, and Table 9-1.
(4) To prevent excess current, the supply voltage difference |VBIAS – VRESET| must be less than specified limit. See GUID-3148EEF2-489E-4025-AD64-40594FE0958A.html#GUID-3148EEF2-489E-4025-AD64-40594FE0958A, GUID-E03635F4-9EAC-4BD0-97AE-23AFBE0EC956.html#DLPS1609748, and Table 9-1.
(5) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, “Low-Power Double Data Rate (LPDDR)” JESD209B.Tester Conditions for VIH and VIL.
  • Frequency = 60 MHz. Maximum Rise Time = 2.5 ns @ (20% – 80%)
  • Frequency = 60 MHz. Maximum Fall Time = 2.5 ns @ (80% – 20%)
(6) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the SCPDO output pin.
(7) The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(11) Simultaneous exposure of the DMD to the maximum #GUID-BE8D87C3-9261-414C-9DA7-46DF77EDAB95 for temperature and UV illumination reduces device lifetime.
(12) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in GUID-1C80258D-88B8-4586-873E-126A31F641ED.html#DLPS1609630 and the package thermal resistance GUID-1C80258D-88B8-4586-873E-126A31F641ED.html#GUID-1C80258D-88B8-4586-873E-126A31F641ED.
(13) Per #DLPS1601904, the maximum operational array temperature must be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. See GUID-CDCCC7DA-506D-4F16-AA89-4F037968E4E5.html#GUID-CDCCC7DA-506D-4F16-AA89-4F037968E4E5 for a definition of micromirror landed duty cycle.
(14) Long-term is defined as the usable life of the device.
(15) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is defined as cumulative time over the usable life of the device and is less than 500 hours.
(16) Temperature difference is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in GUID-1C80258D-88B8-4586-873E-126A31F641ED.html#DLPS1609630. The window test points TP2, TP3, TP4 and TP5 shown in GUID-1C80258D-88B8-4586-873E-126A31F641ED.html#DLPS1609630 are intended to result in the worst case difference temperature. If a particular application causes another point on the window edge to result in a larger difference in temperature, use that point.
(17) DMD is qualified at the combination of the maximum temperature and maximum lumens specified. Operation of the DMD outside of these limits has not been tested.
(18) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(19) The locations of Thermal Test Points TP2, TP3, TP4 and TP5 in Figure 10 are intended to measure the highest window edge temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular application causes additional points on the window edge to be at a higher temperature, add those test points
(20) Limit exposure to dew point temperatures in the elevated range during storage and operation to less than a total cumulative time of CTELR.
(21) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document, and may negatively affect lifetime.
GUID-E47D1640-BD02-4BCD-9A42-A9E55B3E6BBF-low.gif Figure 6-1 Maximum Recommended Array Temperature - Derating Curve