DLPS097B August   2017  – January 2025 DLP650NE

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements
    8. 5.8  Window Characteristics
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Chipset Component Usage Specification
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On or Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On or Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8.   Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
  9. Power Supply Requirements
    1. 7.1 DMD Power Supply Requirements
    2. 7.2 DMD Power Supply Power-Up Procedure
    3. 7.3 DMD Power Supply Power-Down Procedure
  10. Device Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Device Support
      1. 8.2.1 Device Nomenclature
      2. 8.2.2 Device Markings
    3. 8.3 Documentation Support
      1. 8.3.1 Related Documentation
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  11. Revision History
  12. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FYE|350
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
VOH High-level output voltage VCC = 3.3 V, IOH = –20 mA 2.4 V
VOL Low -level output voltage VCC = 3.45 V, IOL = 15 mA 0.4 V
IIH High-level input current(2)(3) VCC = 3.45 V, VI = VCC 250 µA
IlL Low-level input current VCC = 3.45 V, VI = 0 –250 µA
IOZ High–impedance output current VCC = 3.45 V 10 µA
ICC Supply current(4) VCC = 3.45 V 1100 mA
ICCI VCCI = 3.45 V 500
IOFFSET Supply current(5) VOFFSET = 8.75 V 10 25 mA
IBIAS VBIAS = 16.5 V 10 14
IRESET Supply current VRESET = –10.5 V 10 11 mA
ITOTAL Total Sum 1650
CI Input capacitance ƒ = 1 MHz 10 pF
CO Output capacitance ƒ = 1 MHz 10 pF
CM Reset group capacitance MBRST(14:0) ƒ = 1 MHz

all inputs interconnected,

(1920 x 1080) array 
330 390 pF
All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
Applies to LVCMOS input pins only; excludes the LVDS pins and MBRST pins
LVCMOS input pins utilize an internal 18000-Ω passive resistor for pullup and pulldown configurations. Refer to Section 4 to determine the pullup or pulldown configuration used.
To prevent excess current, the supply voltage change |VCCI – VCC| must be less than specified limit.
To prevent excess current, the supply voltage change |VBIAS – VOFFSET| must be less than specified limit.