DLPS097A August   2017  – February 2023 DLP650NE

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Window Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On or Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On or Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
        1.       Application and Implementation
          1. 8.1 Application Information
          2. 8.2 Typical Application
            1. 8.2.1 Design Requirements
            2. 8.2.2 Detailed Design Procedure
  8. 8 Power Supply Requirements
    1. 8.1 DMD Power Supply Requirements
    2. 8.2 DMD Power Supply Power-Up Procedure
    3. 8.3 DMD Power Supply Power-Down Procedure
  9. 9 Device Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Device Support
      1. 9.2.1 Device Nomenclature
      2. 9.2.2 Device Markings
    3. 9.3 Documentation Support
      1. 9.3.1 Related Documentation
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FYE|350
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.
MINNOMMAXUNIT
SUPPLY VOLTAGES#DLPS0363784#DLPS0368910
VCCSupply voltage for LVCMOS core logic3.153.33.45V
VCCISupply voltage for LVDS receivers3.153.33.45V
VOFFSETSupply voltage for HVCMOS and micromirror electrodes#DLPS03689108.258.58.75V
VBIASSupply voltage for micromirror electrodes15.51616.5V
VRESETSupply voltage for micromirror electrodes–9.5–10–10.5V
|VCCI–VCC|Supply voltage change (absolute value)#DLPS036922000.3V
|VBIAS–VOFFSET|Supply voltage change (absolute value)#DLPS03635918.75V
LVCMOS PINS
VIHHigh level Input voltage#DLPS03687471.72.5VCC + 0.15V
VILLow level Input voltage#DLPS0368747– 0.30.7V
IOHHigh level output current at VOH = 2.4 V–20mA
IOLLow level output current at VOL = 0.4 V15mA
tPWRDNZPWRDNZ pulse width#DLPS036205410ns
SCP INTERFACE
ƒSCPCLKSCP clock frequency#DLPS0368179500kHz
tSCP_DSSCPDI clock setup time (before SCPCLK falling-edge)#DLPS0365472800ns
tSCP_DHSCPDI hold time (after SCPCLK falling-edge)#DLPS0365472900ns
tSCP_BYTE_INTERVALTime between consecutive bytes1µs
tSCP_NEG_ENZTime between falling edge of SCPENZ and the first rising edge of SCPCLK30ns
tSCP_PW_ENZSCPENZ inactive pulse width (high level)1µs
tSCP_OUT_ENTime required for SCP output buffer to recover after SCPENZ (from tristate)1.5ns
ƒclockSCP circuit clock oscillator frequency#DLPS03632889.611.1MHz
LVDS INTERFACE
ƒclockClock frequency for LVDS interface, DCLK (all channels)400MHz
|VID|Input differential voltage (absolute value)#DLPS0361637100400600mV
VCMCommon mode#DLPS03616371200mV
VLVDSLVDS voltage#DLPS036163702000mV
tLVDS_RSTZTime required for LVDS receivers to recover from PWRDNZ10ns
ZINInternal differential termination resistance95105Ω
ZLINELine differential impedance (PWB/trace)90100110Ω
ENVIRONMENTAL
TARRAYArray temperature, long-term operational#DLPS0361000#DLPS0364991#DLPS05316241040 to 70#DLPS0368123°C
Array temperature, short-term operational#DLPS0364991#DLPS0531017010
TWINDOWWindow temperature – operational#DLPS053630185°C
T|DELTA |Absolute temperature delta between any point on the window edge and the ceramic test point TP1.#DLPS0539398#T4931159-3826°C
TDP-AVGAverage dew point temperature (non-condensing)#DLPS053101528°C
TDP-ELRElevated dew point temperature range (non-condensing)#DLPS05310162836°C
CTELRCumulative time in elevated dew point temperature range24Months
LOperating system luminance#T4931159-384200lm
ILLUVIllumination, wavelength < 395 nm#DLPS03610000.682.0mW/cm2
ILLVISIllumination, wavelength between 395 nm and 800 nmThermally Limited
ILLIRIllumination, wavelength > 800 nm10mW/cm2
(1) Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified max voltages.
(3) To prevent excess current, the supply voltage change |VCCI – VCC| must be less than specified limit.
(4) To prevent excess current, the supply voltage change |VBIAS – VOFFSET| must be less than specified limit. Refer to GUID-BF8932C9-DEB7-4A58-B11F-B89013211970.html#GUID-BF8932C9-DEB7-4A58-B11F-B89013211970 for additional information.
(5) Tester conditions for VIH and VIL:
Frequency = 60 MHz. Maximum Rise Time = 2.5 ns at (20% to 80%)
Frequency = 60 MHz. Maximum Fall Time = 2.5 ns at (80% to 20%)
(6) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the SCPDO output pin.
(7) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(9) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.
(11) Simultaneous exposure of the DMD to the maximum #GUID-A63A6657-2017-47E9-A521-822BBCE95149 for temperature and UV illumination reduces device lifetime.
(12) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in GUID-BF92E501-4F17-4FB7-BC6C-0F10927887E0.html#DLPS0363628 and the package thermal resistance using the calculation in GUID-BF92E501-4F17-4FB7-BC6C-0F10927887E0.html#GUID-BF92E501-4F17-4FB7-BC6C-0F10927887E0.
(13) Long-term is defined as the average over the usable life.
(14) Per #T4931159-39, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. See GUID-F9E94139-0805-44B1-828E-3378D693120C.html#GUID-F9E94139-0805-44B1-828E-3378D693120C.
(15) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is defined as cumulative time over the usable life of the device and is less than 500 hours.
(16) The locations of thermal test points TP2, TP3, TP4 and TP5 in GUID-BF92E501-4F17-4FB7-BC6C-0F10927887E0.html#DLPS0363628 are intended to measure the highest window edge temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.
(17) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in GUID-BF92E501-4F17-4FB7-BC6C-0F10927887E0.html#DLPS0363628. The window test points TP2, TP3, TP4, and TP5 shown in GUID-BF92E501-4F17-4FB7-BC6C-0F10927887E0.html#DLPS0363628 are intended to result in the worst-case delta temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that point should be used.
(18) DMD is qualified at the combination of the maximum temperature and maximum lumens specified. Operation of the DMD outside of these limits has not been tested.
(19) The average over time (including storage and operating) that the device is not in the 'elevated dew point temperature range'.
(20) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CTELR.
GUID-E47D1640-BD02-4BCD-9A42-A9E55B3E6BBF-low.gifFigure 6-1 Recommended Maximum DMD Temperature—Derating Curve