DLPS097 Data sheet

DLPS097A August 2017 – February 2023 DLP650NE

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

FYE|350

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.7 Timing Requirements

Over Recommended Operating Conditions (GUID-A63A6657-2017-47E9-A521-822BBCE95149.html#GUID-A63A6657-2017-47E9-A521-822BBCE95149) unless otherwise noted.#T4931159-11

		DESCRIPTION#DLPS0367132		MIN	TYP	MAX	UNIT
SCP INTERFACE#DLPS0367351
t_r	Rise time	20% to 80% reference points				200	ns
t_ƒ	Fall time	80% to 20% reference points				200	ns
LVDS INTERFACE#DLPS0367351
t_r	Rise time	20% to 80%		100		400	ps
t_ƒ	Fall time	80% to 20%		100		400	ps
LVDS CLOCKS#DLPS0361546
t_c	Cycle time	DCLK_A, 50% to 50%		2.5			ns
t_c	Cycle time	DCLK_B, 50% to 50%		2.5			ns
t_w	Pulse duration	DCLK_A, 50% to 50%		1.19	1.25		ns
t_w	Pulse duration	DCLK_B, 50% to 50%		1.19	1.25		ns
LVDS INTERFACE#DLPS0361546
t_su	Setup time	D_A(15:0) before rising or falling edge of DCLK_A		0.1			ns
t_su	Setup time	D_B(15:0) before rising or falling edge of DCLK_B		0.1			ns
t_su	Setup time	SCTRL_A before rising or falling edge of DCLK_A		0.1			ns
t_su	Setup time	SCTRL_B before rising or falling edge of DCLK_B		0.1			ns
t_h	Hold time	D_A(15:0) after rising or falling edge of DCLK_A		0.4			ns
t_h	Hold time	D_B(15:0) after rising or falling edge of DCLK_B		0.4			ns
t_h	Hold time	SCTRL_A after rising or falling edge of DCLK_A		0.3			ns
t_h	Hold time	SCTRL_B after rising or falling edge of DCLK_B		0.3			ns
LVDS INTERFACE#DLPS0365440
t_skew	Skew time	Channel B relative to Channel A#DLPS0365440	Channel A includes the following LVDS pairs: DCLK_AP and DCLK_AN SCTRL_AP and SCTRL_AN D_AP(15:0) and D_AN(15:0)	–1.25		1.25	ns
t_skew	Skew time	Channel B relative to Channel A#DLPS0365440	Channel B includes the following LVDS pairs: DCLK_BP and DCLK_BN SCTRL_BP and SCTRL_BN D_BP(15:0) and D_BN(15:0)	–1.25		1.25	ns

(1) Refer to GUID-E7B7574C-B5FF-45F3-A720-D3CAB64A881F.html#GUID-E7B7574C-B5FF-45F3-A720-D3CAB64A881F for pin details.

(2) Refer to #DLPS0362069.

(3) Refer to #DLPS0364643.

(4) Refer to #DLPS0362502.

(5) Tested at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be considered.

Not to scale

Refer to the SCP Interface section of the Recommended Operating Conditions GUID-A63A6657-2017-47E9-A521-822BBCE95149.html#GUID-A63A6657-2017-47E9-A521-822BBCE95149.

Figure 6-2 SCP Timing Parameters

Refer to the LVDS Interface section of the Recommended Operating Conditions (GUID-A63A6657-2017-47E9-A521-822BBCE95149.html#GUID-A63A6657-2017-47E9-A521-822BBCE95149).

Refer to the Pin Functions table for the list of LVDS pins.

Figure 6-3 LVDS Voltage Definitions (References)

Not to scale

Refer to the LVDS Interface section of the Recommended Operating Conditions (GUID-A63A6657-2017-47E9-A521-822BBCE95149.html#GUID-A63A6657-2017-47E9-A521-822BBCE95149).

Figure 6-4 LVDS Voltage Parameters

Refer to the LVDS Interface section of the Recommended Operating Conditions (GUID-A63A6657-2017-47E9-A521-822BBCE95149.html#GUID-A63A6657-2017-47E9-A521-822BBCE95149).

Refer to the Pin Functions table for the list of LVDS pins.

Figure 6-5 LVDS Equivalent Input Circuit

Not to scale

Refer to the timing requirements.

Refer to the Pin Functions table for the list of LVDS pins and SCP pins.

Figure 6-6 Rise Time and Fall Time

Figure 6-7 Test Load Circuit for Output Propagation Measurement

For output timing analysis, the tester pin electronics and its transmission line effects must be considered. System design should use IBIS or other simulation tools to correlate the timing reference load to a system environment. See #T4931159-36.

Not to scale

Refer to the LVDS Interface section in the timing requirements.

Figure 6-8 Timing Requirement Parameter Definitions

Not to scale

Refer to the LVDS Interface section in the timing requirements.

Figure 6-9 LVDS Interface Channel Skew Definition