DLPS153 October   2023 DLP651LE

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  System Mounting Interface Loads
    9. 6.9  Micromirror Array Physical Characteristics
    10. 6.10 Micromirror Array Optical Characteristics
    11. 6.11 Window Characteristics
    12. 6.12 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Optical Interface and System Image Quality Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill
    5. 7.5 Micromirror Array Temperature Calculation
    6. 7.6 Micromirror Power Density Calculation
    7. 7.7 Window Aperture Illumination Overfill Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
      1. 9.2.1 Layers
      2. 9.2.2 Impedance Requirements
      3. 9.2.3 Trace Width, Spacing
  11. 10Power Supply Recommendations
    1. 10.1 DMD Power Supply Power-Up Procedure
    2. 10.2 DMD Power Supply Power-Down Procedure
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • FYM|149
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High level output voltage VCC = 3 V, IOH = – 20 mA 2.4 V
VOL Low level output voltage VCC = 3.6 V, IOL = 15 mA 0.4 V
IOZ High impedance output current VCC = 3.6 V 10 µA
IIL Low level input current VCC = 3.6 V, VI = 0 –60 µA
IIH High level input current (1) VCC = 3.6 V, VI = VCC 200 µA
ICC Supply current VCC (2) VCC = 3.6 V 479 mA
ICCI Supply current VCCI (2) VCCI = 3.6 V 309 mA
IOFFSET Supply current VOFFSET (3) VOFFSET = 8.75 V 25 mA
ZIN Internal differential termination resistance 95 105 Ω
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
CI Input capacitance(1) f = 1 MHz 10 pF
CO Output capacitance(1) f = 1 MHz 10 pF
CIM Input capacitance for MBRST[0:15] pins f = 1 MHz

200

330

 pF
(1) Applies to LVCMOS pins only. Excludes LVDS pins and test pad pins
(2) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than the specified limit in Section 6.4.
(3) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit in Section 6.4.