DLPS163D April   2019  – December 2023 DLP660TE

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions—Test Pads
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Capacitance at Recommended Operating Conditions
    8. 5.8  Timing Requirements
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Optical Interface and System Image Quality
        1. 6.5.1.1 Numerical Aperture and Stray Light Control
        2. 6.5.1.2 Pupil Match
        3. 6.5.1.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 DMD Die Temperature Sensing
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
      1. 9.2.1 Layers
      2. 9.2.2 Impedance Requirements
      3. 9.2.3 Trace Width, Spacing
        1. 9.2.3.1 Voltage Signals
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2 DMD Power Supply Power-Down Procedure

  • During power-down, VCC and VCCI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within the specified limit of ground. See Table 8-1.
  • During power-down, it is a strict requirement that the voltage delta between VBIAS and VOFFSET must be within the specified limit shown in Section 5.4.
  • During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS.
  • Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements specified in Section 5.1, in Section 5.4, and in Figure 8-1.
  • During power-down, LVCMOS input pins must be less than specified in Section 5.4.
GUID-2A32A1AB-3E6A-4FBD-8319-119EA414A2F6-low.jpgFigure 8-1 DMD Power Supply Requirements
  1. See Section 4 and Section 5.4.
  2. To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit in Section 5.4.
  3. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in Section 5.4.
  4. To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit in Section 5.4.
  5. VBIAS must power up after VOFFSET has powered up, per the Delay1 specification in Table 8-1.
  6. PG_OFFSET must turn off after EN_OFFSET has turned off, per the Delay2 specification in Table 8-1.
  7. DLP controller software enables the DMD power supplies to turn on after RESET_OEZ is at logic high.
  8. DLP controller software initiates the global VBIAS command.
  9. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates PWRDNZ and disables VBIAS, VRESET and VOFFSET.
  10. Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware, EN_OFFSET may turn off after PG_OFFSET has turned off. The OEZ signal goes high prior to PG_OFFSET turning off to indicate the DMD micromirror has completed the emergency park procedures.
Table 8-1 DMD Power-Supply Requirements
PARAMETER DESCRIPTION MIN NOM MAX UNIT
Delay1 Delay from VOFFSET settled at recommended operating voltage to VBIAS and VRESET power up 1 2 ms
Delay2 PG_OFFSET hold time after EN_OFFSET goes low 100 ns