DLPS241 april   2023 DLP670RE

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  System Mounting Interface Loads
    9. 6.9  Micromirror Array Physical Characteristics
    10. 6.10 Micromirror Array Optical Characteristics
    11. 6.11 Window Characteristics
    12. 6.12 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On or Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On or Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Requirements
    1. 9.1 DMD Power Supply Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Power Supply Power-Down Procedure
  10. 10Device Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FYE|350
Thermal pad, mechanical data (Package|Pins)

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.
MIN NOM MAX UNIT
SUPPLY VOLTAGES(1)(2)
VCC Supply voltage for LVCMOS core logic 3.15 3.3 3.45 V
VCCI Supply voltage for LVDS receivers 3.15 3.3 3.45 V
VOFFSET Supply voltage for HVCMOS and micromirror electrodes(2) 8.25 8.5 8.75 V
VBIAS Supply voltage for micromirror electrodes 15.5 16 16.5 V
VRESET Supply voltage for micromirror electrodes –9.5 –10 –10.5 V
|VCCI–VCC| Supply voltage change (absolute value)(3) 0 0.3 V
|VBIAS–VOFFSET| Supply voltage change (absolute value)(4) 8.75 V
LVCMOS PINS
VIH High level Input voltage(5) 1.7 2.5 VCC + 0.15 V
VIL Low level Input voltage(5) –0.3 0.7 V
IOH High level output current at VOH = 2.4 V –20 mA
IOL Low level output current at VOL = 0.4 V 15 mA
tPWRDNZ PWRDNZ pulse width(6) 10 ns
SCP INTERFACE
ƒSCPCLK SCP clock frequency(7) 500 kHz
tSCP_DS SCPDI clock setup time (before SCPCLK falling-edge)(8) 800 ns
tSCP_DH SCPDI hold time (after SCPCLK falling-edge)(8) 700 ns
tSCP_BYTE_INTERVAL Time between consecutive bytes 1 µs
tSCP_NEG_ENZ Time between falling edge of SCPENZ and the first rising edge of SCPCLK 30 ns
tSCP_PW_ENZ SCPENZ inactive pulse width (high level) 1 µs
tSCP_OUT_EN Time required for SCP output buffer to recover after SCPENZ (from tristate) 1.5 ns
ƒclock SCP circuit clock oscillator frequency (9) 9.6 11.1 MHz
LVDS INTERFACE
ƒclock Clock frequency for LVDS interface, DCLK (all channels) 400 430 MHz
|VID| Input differential voltage (absolute value)(10) 200 400 600 mV
VCM Common mode(10) 1200 mV
VLVDS LVDS voltage(10) 0 2000 mV
tLVDS_RSTZ Time required for LVDS receivers to recover from PWRDNZ 10 ns
ZIN Internal differential termination resistance 95 105 Ω
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
ENVIRONMENTAL
TARRAY Array temperature, long-term operational(11)(12)(13)(14) 10 40 to 70(14) °C
Array temperature, short-term operational 500-hr max(12)(15) 0 10
TWINDOW Window temperature – operational(16) 85 °C
T|DELTA | Absolute temperature delta between any point on the window edge and the ceramic test point TP1.(17) 15 °C
TDP-AVG Average dew point temperature (non-condensing)(18) 28 °C
TDP-ELR Elevated dew point temperature range (non-condensing)(19) 28 36 °C
CTELR Cumulative time in elevated dew point temperature range 24 Months
LAMP
ILLUV Illumination, wavelength < 395 nm(11) 0.68 2.0 mW/cm2
ILLVIS Illumination, wavelength between 395 nm and 800 nm(20) 29.3 W/cm2
ILLIR Illumination, wavelength > 800 nm 10 mW/cm2
SOLID STATE
ILLUV Illumination, wavelength < 410 nm(11) 0.45 mW/cm2
ILLVIS Illumination, wavelength between 410 nm and 800 nm (20) 34.7 W/cm2
ILLIR Illumination, wavelength > 800 nm 10 mW/cm2
(1) Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified max voltages.
(3) To prevent excess current, the supply voltage change |VCCI – VCC| must be less than specified limit.
(4) To prevent excess current, the supply voltage change |VBIAS – VOFFSET| must be less than specified limit. Refer to Section 9 for additional information.
(5) Tester conditions for VIH and VIL:
Frequency = 60 MHz. Maximum Rise Time = 2.5 ns at (20% to 80%)
Frequency = 60 MHz. Maximum Fall Time = 2.5 ns at (80% to 20%)
(6) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the SCPDO output pin.
(7) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(8) Refer to Figure 6-2.
(9) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.
(10) Refer to Figure 6-3, Figure 6-4, and Figure 6-5.
(11) Simultaneous exposure of the DMD to the maximum Section 6.4 for temperature and UV illumination reduces device lifetime.
(12) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 7-1 and the package thermal resistance using the calculation in Section 7.6.
(13) Long-term is defined as the average over the usable life.
(14) Per Figure 6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. See Section 7.7.
(15) Short-term is the total cumulative time over the useful life of the device.
(16) The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 7-1 are intended to measure the highest window edge temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.
(17) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to result in the worst-case delta temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that point should be used.
(18) The average over time (including storage and operating) that the device is not in the 'elevated dew point temperature range'.
(19) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CTELR.
(20) The maximum optical power that can be incident on the DMD is limited by the maximum optical power density and the micromirror array temperature.
GUID-FB0E7B60-702F-4785-B150-C49C4F8DA327-low.gifFigure 6-1 Recommended Maximum DMD Temperature—Derating Curve