DLPS096B November   2017  – May 2022 DLPC120-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 LED Driver Interface
    2. 5.2 DMD Temperature Interface
    3.     General Purpose I/O
    4. 5.3 Main Video and Data Control Interface
    5. 5.4 DMD Interface
    6. 5.5 Memory Interface
    7.     Board Level Test and Debug
    8.     Manufacturing Test Support
    9.     Test Point Interface
    10.     Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics for I/O
    7. 6.7  Power Supply and Reset Timing Requirements
    8. 6.8  Reference Clock PLL Timing Requirements
    9. 6.9  Parallel Interface General Timing Requirements
    10. 6.10 Parallel Interface Frame Timing Requirements
    11. 6.11 Flash Memory Interface Timing Requirements
    12. 6.12 DMD Interface Timing Requirements
    13. 6.13 JTAG Interface Timing Requirements
    14. 6.14 I2C Interface Timing Requirements
  7. 7 Parameter Measurement Information
    1. 7.1 Parallel Interface Input Source Timing
    2. 7.2 Design for Test Functions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Flash Interface
      2. 8.3.2 Serial Flash Programming
      3. 8.3.3 DDR2 Memory Interface
      4. 8.3.4 JTAG and DMD Interface Test
      5. 8.3.5 Temperature Monitor Function
      6. 8.3.6 Host Command Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Video Mode
      2. 8.4.2 Splash Screen Mode
      3. 8.4.3 Test Pattern Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB layout guidelines for internal ASIC PLL power
      2. 11.1.2 DLPC120-Q1 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 PCB Routing Guidelines
      5. 11.1.5 Number of Layer Changes
      6. 11.1.6 Terminations
      7. 11.1.7 General Handling Guidelines for Unused CMOS-Type Pins
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Device Support
      1. 12.2.1 Device Nomenclature
        1. 12.2.1.1 Device Markings
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZXS|216
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-F686A35F-EEF4-4DC6-96A7-C8F1E4A8BEFA-low.pngFigure 5-1 ZXS Package216-Pin BGATop View
Table 5-1 DLPC120-Q1 Device Initialization and Programming Pin Descriptions
PINI/OI/OCLOCK
NAMENO.POWERTYPESYSTEMDESCRIPTION
RESETZH13 3.30 VI2AsyncFunctional Reset (Active Low). Resets internal logic and causes PLL startup and PLL locking. Assertion is required after power supplies are within limits. See Section 6.7 for timing requirements.
PWRGOODG13I2AsyncSystem Power Good indicator. Should be held low until all DLPC120-Q1 power has been within operating limits. See Section 6.7 for timing requirements. Must be set high to enable normal operation. When set low, the DLPC120-Q1 begins the parking routine for the DMD. Together with pin E14 (LED_R_PWM / PWRGOOD_CNTRL), this signal is critical for DLP30xx-Q1 parking as part of the Pre-Conditioning Sequence and subsequent un-parking. See DLPC120-Q1 Programmer's Guide for implementation details.
PLL_REFCLK_IG15I2N/AReference Clock Input (16 MHz). Can be driven by crystal across this pin and PLL_REFCLK_O or by external oscillator. See Section 6.7 for timing requirements.
PLL_REFCLK_OG14O6N/ACrystal output. Used with PLL_REFCLK_I.
HUD_INTRA14O6N/AInterrupt signal. This active high signal indicates one of the interrupt sources in the controller has been triggered.
IIC_SCL_1P16B8N/AI2C Clock for Device configuration and control. Requires external pull-up. Port 1 peripheral command/control interface.
IIC_SDA_1N15B8N/AI2C Data for Device configuration and control. Requires external pull-up. Port 1 peripheral command/control interface.
IIC_SCL_2M15B8N/AI2C Clock Debug Port. Requires external pull-up. Port 2 peripheral command/control interface.
IIC_SDA_2N16B8N/AI2C Data Debug Port. Requires external pull-up. Port 2 peripheral command/control interface.
FLASH_POCIF14I2FLASH_SCLKSerial Data input from the external SPI Flash device. This provides device logical programming data as well as functional configuration parameter data.
FLASH_CSZF15O6FLASH_SCLKChip Select output for the external SPI Flash device. Active low.
FLASH_SCLKE16O6N/AClock for the external SPI Flash device.
FLASH_PICOE15O6FLASH_SCLKSerial Data output to the external SPI Flash device. This pin sends address and control information as well as data when programming.