DLPS029F
April 2013 – May 2019
DLPC350
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Simplified Application
4
Revision History
5
Pin Configuration and Functions
Pin Functions
Table 1.
Power and Ground Pin Descriptions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
I/O Electrical Characteristics
6.6
I2C0 and I2C1 Interface Timing Requirements
6.7
Port 1 Input Pixel Interface Timing Requirements
6.8
Port 2 Input Pixel Interface (FPD-Link Compatible LVDS Input) Timing Requirements
6.9
System Oscillator Timing Requirements
6.10
Reset Timing Requirements
6.11
Video Timing Input Blanking Specification
6.11.1
Source Input Blanking
6.12
Programmable Output Clocks Switching Characteristics
6.13
DMD Interface Switching Characteristics
6.14
JTAG Interface: I/O Boundary Scan Application Switching Characteristics
7
Parameter Measurement Information
7.1
Power Consumption
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Board Level Test Support
8.4
Device Functional Modes
8.4.1
Structured Light Applications
8.4.2
(LVDS) Receiver Supported Pixel Mapping Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Typical Chipset Application
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
DLPC350 System Interfaces
9.2.1.2.1.1
Control Interface
9.2.1.2.1.2
Input Data Interface
9.2.1.2.2
DLPC350 System Output Interfaces
9.2.1.2.2.1
Illumination Interface
9.2.1.2.2.2
Trigger Interface (Sync Outputs)
9.2.1.2.3
DLPC350 System Support Interfaces
9.2.1.2.3.1
Reference Clock
9.2.1.2.3.2
PLL
9.2.1.2.3.3
Program Memory Flash Interface
9.2.1.2.4
DMD Interfaces
9.2.1.2.4.1
DLPC350 to DMD Digital Data
9.2.1.2.4.2
DLPC350 to DMD Control Interface
9.2.1.2.4.3
DLPC350 to DMD Micromirror Reset Control Interface
10
Power Supply Recommendations
10.1
System Power and Reset
10.1.1
Default Conditions
10.1.1.1
1.2-V System Power
10.1.1.2
1.8-V System Power
10.1.1.3
1.9-V System Power
10.1.1.4
3.3-V System Power
10.1.1.5
FPD-Link Input LVDS System Power
10.1.2
System Power-up and Power-down Sequence
10.1.3
Power-On Sense (POSENSE) Support
10.1.4
Power-Good (PWRGOOD) Support
10.1.5
5-V Tolerant Support
10.1.6
Power Reset Operation
10.1.7
System Reset Operation
11
Layout
11.1
Layout Guidelines
11.1.1
DMD Interface Design Considerations
11.1.2
DMD Termination Requirements
11.1.3
Decoupling Capacitors
11.1.4
Power Plane Recommendations
11.1.5
Signal Layer Recommendations
11.1.6
General Handling Guidelines for CMOS-Type Pins
11.1.7
PCB Manufacturing
11.1.7.1
General Guidelines
11.1.7.2
Trace Widths and Minimum Spacings
11.1.7.3
Routing Constraints
11.1.7.4
Fiducials
11.1.7.5
Flex Considerations
11.1.7.6
DLPC350 Thermal Considerations
11.2
Layout Example
11.2.1
Printed Circuit Board Layer Stackup Geometry
11.2.2
Recommended DLPC350 MOSC Crystal Oscillator Configuration
11.2.3
Recommended DLPC350 PLL Layout Configuration
12
Device and Documentation Support
12.1
Device Support
12.1.1
Video Timing Parameter Definitions
12.1.2
Device Nomenclature
12.1.3
Device Marking
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Trademarks
12.4
Glossary
13
Mechanical, Packaging, and Orderable Information
13.1
Package Option Addendum
13.1.1
Packaging Information
Package Options
Mechanical Data (Package|Pins)
ZFF|419
MPBGAF9
Thermal pad, mechanical data (Package|Pins)
7
Parameter Measurement Information