DLPS024G August   2012  – February 2020 DLPC410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 Binary Pattern Data Path
        1. 8.3.1.1  DIN_A, DIN_B, DIN_C, DIN_D Input Data Buses
        2. 8.3.1.2  DCLKIN Input Clocks
        3. 8.3.1.3  DVALID Input Signals
        4. 8.3.1.4  DOUT_A, DOUT_B, DOUT_C, DOUT_D Output Data Buses
        5. 8.3.1.5  DCLKOUT Output Clocks
        6. 8.3.1.6  SCTRL Output Signals
        7. 8.3.1.7  Supported DMD Bus Sizes
        8. 8.3.1.8  Row Cycle definition
        9. 8.3.1.9  DLP9500 and DLP9500UV Input Data Formatting
        10. 8.3.1.10 DLP7000 and DLP7000UV Input Data Bus
        11. 8.3.1.11 DLP650LNIR Input Data Bus
      2. 8.3.2 Data Bus Operations
        1. 8.3.2.1 Row Addressing
        2. 8.3.2.2 Single Row Write Operation
        3. 8.3.2.3 No-Op Row Cycle Description
      3. 8.3.3 DMD Block Operations
        1. 8.3.3.1 Mirror Clocking Pulse (MCP)
        2. 8.3.3.2 Reset Active (RST_ACTIVE)
        3. 8.3.3.3 DMD Block Control Signals
          1. 8.3.3.3.1 Block Mode - BLK_MD1:0)
          2. 8.3.3.3.2 Block Address - BLK_AD(3:0)
          3. 8.3.3.3.3 Reset 2 Blocks - RST2BLK
        4. 8.3.3.4 DMD Block Operations
          1. 8.3.3.4.1 Global Reset (MCP) Consideration
      4. 8.3.4 Other Data Control Inputs
        1. 8.3.4.1 Complement Data
        2. 8.3.4.2 North/South Flip
      5. 8.3.5 Miscellaneous Control Inputs
        1. 8.3.5.1 ARST
        2. 8.3.5.2 CLKIN_R
        3. 8.3.5.3 DMD_A_RESET
        4. 8.3.5.4 Watchdog Timer Enable (WDT_ENABLE)
      6. 8.3.6 Miscellaneous Status Outputs
        1. 8.3.6.1 INIT_ACTIVE
        2. 8.3.6.2 DMD_Type(3:0)
        3. 8.3.6.3 DDC_VERSION(2:0)
        4. 8.3.6.4 LED0
        5. 8.3.6.5 LED1
        6. 8.3.6.6 DLPA200 Control Signals
        7. 8.3.6.7 ECM2M_TP_ (31:0)
    4. 8.4 Device Functional Modes
      1. 8.4.1 DLPC410 Initialization and Training
        1. 8.4.1.1 Initialization
        2. 8.4.1.2 Input Data Interface (DIN) Training
      2. 8.4.2 DLPC410 Operational Modes
        1. 8.4.2.1 Single Block Mode
        2. 8.4.2.2 Single Block Phased Mode
        3. 8.4.2.3 Dual Block Mode
        4. 8.4.2.4 Quad Block Mode
        5. 8.4.2.5 Global Mode
        6. 8.4.2.6 DMD Park Mode
        7. 8.4.2.7 DMD Idle Mode
      3. 8.4.3 LOAD4 Functionality (enabled with DLPR410A)
        1. 8.4.3.1 Enabling LOAD4
        2. 8.4.3.2 Loading Data with LOAD4
        3. 8.4.3.3 Row Mapping with LOAD4
        4. 8.4.3.4 Using Block Clear with LOAD4
        5. 8.4.3.5 Timing Requirements for LOAD4
        6. 8.4.3.6 Global Binary Pattern Rate increases using LOAD4
        7. 8.4.3.7 Special LOAD4 considerations
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Description
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Setup
      1. 9.3.1 Debugging Guidelines
      2. 9.3.2 Initialization
        1. 9.3.2.1 Input Data Bus Calibration
        2. 9.3.2.2 DLPA200 Initialization Step 1
        3. 9.3.2.3 DMD Initialization
          1. 9.3.2.3.1 DMD Device ID Check
        4. 9.3.2.4 DLPA200 Initialization Step 2
        5. 9.3.2.5 Command Sequence Initialization
      3. 9.3.3 Image Display Issues
        1. 9.3.3.1 Present Data to DLPC410
        2. 9.3.3.2 Load Data to DMD
        3. 9.3.3.3 Mirror Clocking Pulse
  10. 10Power Supply Recommendations
    1. 10.1 Power Down Operation
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
      4. 11.1.4 PCB Layout Guidelines
        1. 11.1.4.1 DMD Interface
          1. 11.1.4.1.1 Trace Length Matching
        2. 11.1.4.2 DLPC410 DMD Decoupling
          1. 11.1.4.2.1 Decoupling Capacitors
        3. 11.1.4.3 VCC and VCC2
        4. 11.1.4.4 DMD Layout
        5. 11.1.4.5 DLPA200
    2. 11.2 Layout Example
    3. 11.3 DLPC410 Chipset Connections
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Marking
      2. 12.1.2 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • DLP|676
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.3 DLPC410 Chipset Connections

The following tables list the signal connections between components of the Chipset when used with the DLP650LNIR DMD, the DLP7000 / DLP700UV DMD, and with the DLP9500 / DLP9500UV DMD. These tables do not include power, ground, pull-up, pull-down, termination, or any other connection requirements. Please see the Pin Functions table in the respective data sheet of each chipset component for connection requirements.

Table 22. DLPC410 Chipset Connections with the DLP650LNIR

DLPC410 (CONTROLLER) DLPR410 (PROM) DLPA200 (MICROMIRROR DRIVER) DLP650LNIR (DMD)
PIN PIN PIN PIN
NAME NO. NAME NO. NAME NO. NAME NO.
DONE_DDC K10 CE B4
INTB_DDC J11 OE/RESET A3
PROGB_DDC J18 CF D1
PROM_CCK_DDC J10 CLKOUT C2
PROM_D0_DDC K11 D0 H6
TCK_JTAG U11 TCK H3
TDO_XCF16DDC V11 TDO E6
TMS_JTAG V12 TMS E2
DAD_A_ADDR0 E1 ADDR0 19
DAD_A_ADDR1 E2 ADDR1 18
DAD_A_ADDR2 E3 ADDR2 17
DAD_A_ADDR3 F3 ADDR3 16
DAD_A_MODE0 C1 MODE0 3
DAD_A_MODE1 D1 MODE1 2
DAD_A_SEL0 AB12 SEL0 5
DAD_A_SEL1 AC12 SEL1 4
DAD_A_STROBE AF3 STROBE 15
DAD_INIT AF4 RESET 59
DAD_OE AF5 OE 6
DAD_A_SCPEN AE3 SCPEN 58
SCPCLK AB15 SCPCLK 56 SCPCLK E3
SCPDI AA15 SCPDO 57 SCPDO B2
SCPDO AA14 SCPDI 42 SCPDI F4
DMD_A_SCPEN AB14 SCPEN D4
DMD_A_RESET AD14 PWRDN C3
DDC_DCLKOUT_A_DPN N1 DCLK_AN B22
DDC_DCLKOUT_A_DPP M1 DCLK_AP B24
DDC_DCLKOUT_B_DPN Y5 DCLK_BN AB22
DDC_DCLKOUT_B_DPP Y6 DCLK_BP AB24
DDC_DOUT_A1_DPN AD1 D_AN(1) A13
DDC_DOUT_A1_DPP AE1 D_AP(1) A11
DDC_DOUT_A3_DPN AB1 D_AN(3) C17
DDC_DOUT_A3_DPP AB2 D_AP(3) C15
DDC_DOUT_A5_DPN W1 D_AN(5) A17
DDC_DOUT_A5_DPP Y1 D_AP(5) A19
DDC_DOUT_A7_DPN U1 D_AN(7) D22
DDC_DOUT_A7_DPP U2 D_AP(7) D20
DDC_DOUT_A9_DPN N2 D_AN(9) D28
DDC_DOUT_A9_DPP M2 D_AP(9) B28
DDC_DOUT_A11_DPN K2 D_AN(11) F26
DDC_DOUT_A11_DPP K3 D_AP(11) D26
DDC_DOUT_A13_DPN H2 D_AN(13) H28
DDC_DOUT_A13_DPP J1 D_AP(13) H30
DDC_DOUT_A15_DPN G2 D_AN(15) K26
DDC_DOUT_A15_DPP F2 D_AP(15) K28
DDC_DOUT_B1_DPN AD3 D_BN(1) AC13
DDC_DOUT_B1_DPP AD4 D_BP(1) AC11
DDC_DOUT_B3_DPN AC3 D_BN(3) AA17
DDC_DOUT_B3_DPP AC4 D_BP(3) AA15
DDC_DOUT_B5_DPN AB7 D_BN(5) AC17
DDC_DOUT_B5_DPP AC6 D_BP(5) AC19
DDC_DOUT_B7_DPN AA7 D_BN(7) Y22
DDC_DOUT_B7_DPP Y7 D_BP(7) Y20
DDC_DOUT_B9_DPN W4 D_BN(9) Y28
DDC_DOUT_B9_DPP V4 D_BP(9) AB28
DDC_DOUT_B11_DPN V7 D_BN(11) V26
DDC_DOUT_B11_DPP V6 D_BP(11) Y26
DDC_DOUT_B13_DPN T4 D_BN(13) R29
DDC_DOUT_B13_DPP T5 D_BP(13) T28
DDC_DOUT_B15_DPN U7 D_BN(15) N27
DDC_DOUT_B15_DPP T7 D_BP(15) P26
DDC_SCTRL_AN R1 SCTRL_AN C21
DDC_SCTRL_AP P1 SCTRL_AP C23
DDC_SCTRL_BN AA3 SCTRL_BN AA21
DDC_SCTRL_BP AB4 SCTRL_BP AA23

Table 23. DLPC410 Chipset Connections with the DLP7000

DLPC410 (CONTROLLER) DLPR410 (PROM) DLPA200 (MICROMIRROR DRIVER) DLP7000 / UV (DMD)
PIN PIN PIN PIN
NAME NO. NAME NO. NAME NO. NAME NO.
DONE_DDC K10 CE B4
INTB_DDC J11 OE/RESET A3
PROGB_DDC J18 CF D1
PROM_CCK_DDC J10 CLKOUT C2
PROM_D0_DDC K11 D0 H6
TCK_JTAG U11 TCK H3
TDO_XCF16DDC V11 TDO E6
TMS_JTAG V12 TMS E2
DAD_A_ADDR0 E1 ADDR0 19
DAD_A_ADDR1 E2 ADDR1 18
DAD_A_ADDR2 E3 ADDR2 17
DAD_A_ADDR3 F3 ADDR3 16
DAD_A_MODE0 C1 MODE0 3
DAD_A_MODE1 D1 MODE1 2
DAD_A_SEL0 AB12 SEL0 5
DAD_A_SEL1 AC12 SEL1 4
DAD_A_STROBE AF3 STROBE 15
DAD_INIT AF4 RESET 59
DAD_OE AF5 OE 6
DAD_A_SCPEN AE3 SCPEN 58
SCPCLK AB15 SCPCLK 56 SCPCLK E3
SCPDI AA15 SCPDO 57 SCPDO B2
SCPDO AA14 SCPDI 42 SCPDI F4
DMD_A_SCPEN AB14 SCPEN D4
DMD_A_RESET AD14 PWRDN C3
DDC_DCLKOUT_A_DPN N1 DCLK_AN B22
DDC_DCLKOUT_A_DPP M1 DCLK_AP B24
DDC_DCLKOUT_B_DPN Y5 DCLK_BN AB22
DDC_DCLKOUT_B_DPP Y6 DCLK_BP AB24
DDC_DOUT_A0_DPN AE2 D_AN(0) B10
DDC_DOUT_A0_DPP AF2 D_AP(0) B12
DDC_DOUT_A1_DPN AD1 D_AN(1) A13
DDC_DOUT_A1_DPP AE1 D_AP(1) A11
DDC_DOUT_A2_DPN AC1 D_AN(2) D16
DDC_DOUT_A2_DPP AC2 D_AP(2) D14
DDC_DOUT_A3_DPN AB1 D_AN(3) C17
DDC_DOUT_A3_DPP AB2 D_AP(3) C15
DDC_DOUT_A4_DPN Y2 D_AN(4) B18
DDC_DOUT_A4_DPP AA2 D_AP(4) B16
DDC_DOUT_A5_DPN W1 D_AN(5) A17
DDC_DOUT_A5_DPP Y1 D_AP(5) A19
DDC_DOUT_A6_DPN V1 D_AN(6) A25
DDC_DOUT_A6_DPP V2 D_AP(6) A23
DDC_DOUT_A7_DPN U1 D_AN(7) D22
DDC_DOUT_A7_DPP U2 D_AP(7) D20
DDC_DOUT_A8_DPN R2 D_AN(8) C29
DDC_DOUT_A8_DPP T2 D_AP(8) A29
DDC_DOUT_A9_DPN N2 D_AN(9) D28
DDC_DOUT_A9_DPP M2 D_AP(9) B28
DDC_DOUT_A10_DPN K1 D_AN(10) E27
DDC_DOUT_A10_DPP L2 D_AP(10) C27
DDC_DOUT_A11_DPN K2 D_AN(11) F26
DDC_DOUT_A11_DPP K3 D_AP(11) D26
DDC_DOUT_A12_DPN J3 D_AN(12) G29
DDC_DOUT_A12_DPP H3 D_AP(12) F30
DDC_DOUT_A13_DPN H2 D_AN(13) H28
DDC_DOUT_A13_DPP J1 D_AP(13) H30
DDC_DOUT_A14_DPN H1 D_AN(14) J27
DDC_DOUT_A14_DPP G1 D_AP(14) J29
DDC_DOUT_A15_DPN G2 D_AN(15) K26
DDC_DOUT_A15_DPP F2 D_AP(15) K28
DDC_DOUT_B0_DPN AE5 D_BN(0) AB10
DDC_DOUT_B0_DPP AE6 D_BP(0) AB12
DDC_DOUT_B1_DPN AD3 D_BN(1) AC13
DDC_DOUT_B1_DPP AD4 D_BP(1) AC11
DDC_DOUT_B2_DPN AD5 D_BN(2) Y16
DDC_DOUT_B2_DPP AD6 D_BP(2) Y14
DDC_DOUT_B3_DPN AC3 D_BN(3) AA17
DDC_DOUT_B3_DPP AC4 D_BP(3) AA15
DDC_DOUT_B4_DPN AB5 D_BN(4) AB18
DDC_DOUT_B4_DPP AB6 D_BP(4) AB16
DDC_DOUT_B5_DPN AB7 D_BN(5) AC17
DDC_DOUT_B5_DPP AC6 D_BP(5) AC19
DDC_DOUT_B6_DPN AA5 D_BN(6) AC25
DDC_DOUT_B6_DPP AA4 D_BP(6) AC23
DDC_DOUT_B7_DPN AA7 D_BN(7) Y22
DDC_DOUT_B7_DPP Y7 D_BP(7) Y20
DDC_DOUT_B8_DPN Y3 D_BN(8) AA29
DDC_DOUT_B8_DPP W3 D_BP(8) AC29
DDC_DOUT_B9_DPN W4 D_BN(9) Y28
DDC_DOUT_B9_DPP V4 D_BP(9) AB28
DDC_DOUT_B10_DPN W6 D_BN(10) W27
DDC_DOUT_B10_DPP W5 D_BP(10) AA27
DDC_DOUT_B11_DPN V7 D_BN(11) V26
DDC_DOUT_B11_DPP V6 D_BP(11) Y26
DDC_DOUT_B12_DPN U4 D_BN(12) T30
DDC_DOUT_B12_DPP V3 D_BP(12) U29
DDC_DOUT_B13_DPN T4 D_BN(13) R29
DDC_DOUT_B13_DPP T5 D_BP(13) T28
DDC_DOUT_B14_DPN U6 D_BN(14) R27
DDC_DOUT_B14_DPP U5 D_BP(14) P28
DDC_DOUT_B15_DPN U7 D_BN(15) N27
DDC_DOUT_B15_DPP T7 D_BP(15) P26
DDC_SCTRL_AN R1 SCTRL_AN C21
DDC_SCTRL_AP P1 SCTRL_AP C23
DDC_SCTRL_BN AA3 SCTRL_BN AA21
DDC_SCTRL_BP AB4 SCTRL_BP AA23

Table 24. DLPC410 Chipset Connections with the DLP9500

DLPC410 (CONTROLLER) DLPR410 (PROM) DLPA200 Number 1 (MICROMIRROR DRIVER) DLPA200 Number 2 (MICROMIRROR DRIVER) DLP9500 or UV (DMD)
PIN PIN PIN PIN PIN
NAME NO. NAME NO. NAME NO. NAME NO. NAME NO.
DONE_DDC K10 CE B4
INTB_DDC J11 OE/RESET A3
PROGB_DDC J18 CF D1
PROM_CCK_DDC J10 CLKOUT C2
PROM_D0_DDC K11 D0 H6
TCK_JTAG U11 TCK H3
TDO_XCF16DDC V11 TDO E6
TMS_JTAG V12 TMS E2
DAD_A_ADDR0 E1 ADDR0 19
DAD_A_ADDR1 E2 ADDR1 18
DAD_A_ADDR2 E3 ADDR2 17
DAD_A_ADDR3 F3 ADDR3 16
DAD_A_MODE0 C1 MODE0 3
DAD_A_MODE1 D1 MODE1 2
DAD_A_SEL0 AB12 SEL0 5
DAD_A_SEL1 AC12 SEL1 4
DAD_A_STROBE AF3 STROBE 15
DAD_B_ADDR0 E26 ADDR0 19
DAD_B_ADDR1 E25 ADDR1 18
DAD_B_ADDR2 F25 ADDR2 17
DAD_B_ADDR3 F24 ADDR3 16
DAD_B_MODE0 D26 MODE0 3
DAD_B_MODE1 D25 MODE1 2
DAD_B_SEL0 R22 SEL0 5
DAD_B_SEL1 R23 SEL1 4
DAD_B_STROBE AB20 STROBE 15
DAD_INIT AF4 RESET 59 RESET 59
DAD_OE AF5 OE 6 OE 6
DAD_A_SCPEN AE3 SCPEN 58
DAD_B_SCPEN AB19 SCPEN 58
SCPCLK AB15 SCPCLK 56 SCPCLK 56 SCPCLK AE1
SCPDI AA15 SCPDO 57 SCPDO 57 SCPDO AC3
SCPDO AA14 SCPDI 42 SCPDI 42 SCPDI AD2
DMD_A_SCPEN AB14 SCPEN AD4
DMD_A_RESET AD14 PWRDN B4
DDC_DCLKOUT_A_DPN N1 DCLK_AN D10
DDC_DCLKOUT_A_DPP M1 DCLK_AP D8
DDC_DCLKOUT_B_DPN Y5 DCLK_BN AJ11
DDC_DCLKOUT_B_DPP Y6 DCLK_BP AJ9
DDC_DCLKOUT_C_DPN AA22 DCLK_CN C23
DDC_DCLKOUT_C_DPP AB22 DCLK_CP C21
DDC_DCLKOUT_D_DPN M26 DCLK_DN AJ23
DDC_DCLKOUT_D_DPP M25 DCLK_DP AJ21
DDC_DOUT_A0_DPN AE2 D_AN(0) F2
DDC_DOUT_A0_DPP AF2 D_AP(0) F4
DDC_DOUT_A1_DPN AD1 D_AN(1) H8
DDC_DOUT_A1_DPP AE1 D_AP(1) H10
DDC_DOUT_A2_DPN AC1 D_AN(2) E5
DDC_DOUT_A2_DPP AC2 D_AP(2) E3
DDC_DOUT_A3_DPN AB1 D_AN(3) G9
DDC_DOUT_A3_DPP AB2 D_AP(3) G11
DDC_DOUT_A4_DPN Y2 D_AN(4) D2
DDC_DOUT_A4_DPP AA2 D_AP(4) D4
DDC_DOUT_A5_DPN W1 D_AN(5) G3
DDC_DOUT_A5_DPP Y1 D_AP(5) G5
DDC_DOUT_A6_DPN V1 D_AN(6) E11
DDC_DOUT_A6_DPP V2 D_AP(6) E9
DDC_DOUT_A7_DPN U1 D_AN(7) F8
DDC_DOUT_A7_DPP U2 D_AP(7) F10
DDC_DOUT_A8_DPN R2 D_AN(8) C9
DDC_DOUT_A8_DPP T2 D_AP(8) C11
DDC_DOUT_A9_DPN N2 D_AN(9) H2
DDC_DOUT_A9_DPP M2 D_AP(9) H4
DDC_DOUT_A10_DPN K1 D_AN(10) B10
DDC_DOUT_A10_DPP L2 D_AP(10) B8
DDC_DOUT_A11_DPN K2 D_AN(11) G15
DDC_DOUT_A11_DPP K3 D_AP(11) H14
DDC_DOUT_A12_DPN J3 D_AN(12) D14
DDC_DOUT_A12_DPP H3 D_AP(12) D16
DDC_DOUT_A13_DPN H2 D_AN(13) F14
DDC_DOUT_A13_DPP J1 D_AP(13) F16
DDC_DOUT_A14_DPN H1 D_AN(14) C17
DDC_DOUT_A14_DPP G1 D_AP(14) C15
DDC_DOUT_A15_DPN G2 D_AN(15) H16
DDC_DOUT_A15_DPP F2 D_AP(15) G17
DDC_DOUT_B0_DPN AE5 D_BN(0) AH2
DDC_DOUT_B0_DPP AE6 D_BP(0) AH4
DDC_DOUT_B1_DPN AD3 D_BN(1) AD8
DDC_DOUT_B1_DPP AD4 D_BP(1) AD10
DDC_DOUT_B2_DPN AD5 D_BN(2) AJ5
DDC_DOUT_B2_DPP AD6 D_BP(2) AJ3
DDC_DOUT_B3_DPN AC3 D_BN(3) AE3
DDC_DOUT_B3_DPP AC4 D_BP(3) AE5
DDC_DOUT_B4_DPN AB5 D_BN(4) AG9
DDC_DOUT_B4_DPP AB6 D_BP(4) AG11
DDC_DOUT_B5_DPN AB7 D_BN(5) AE11
DDC_DOUT_B5_DPP AC6 D_BP(5) AE9
DDC_DOUT_B6_DPN AA5 D_BN(6) AH10
DDC_DOUT_B6_DPP AA4 D_BP(6) AH8
DDC_DOUT_B7_DPN AA7 D_BN(7) AF10
DDC_DOUT_B7_DPP Y7 D_BP(7) AF8
DDC_DOUT_B8_DPN Y3 D_BN(8) AK8
DDC_DOUT_B8_DPP W3 D_BP(8) AK10
DDC_DOUT_B9_DPN W4 D_BN(9) AG5
DDC_DOUT_B9_DPP V4 D_BP(9) AG3
DDC_DOUT_B10_DPN W6 D_BN(10) AL11
DDC_DOUT_B10_DPP W5 D_BP(10) AL9
DDC_DOUT_B11_DPN V7 D_BN(11) AE15
DDC_DOUT_B11_DPP V6 D_BP(11) AD14
DDC_DOUT_B12_DPN U4 D_BN(12) AH14
DDC_DOUT_B12_DPP V3 D_BP(12) AH16
DDC_DOUT_B13_DPN T4 D_BN(13) AF14
DDC_DOUT_B13_DPP T5 D_BP(13) AF16
DDC_DOUT_B14_DPN U6 D_BN(14) AJ17
DDC_DOUT_B14_DPP U5 D_BP(14) AJ15
DDC_DOUT_B15_DPN U7 D_BN(15) AD16
DDC_DOUT_B15_DPP T7 D_BP(15) AE17
DDC_DOUT_C0_DPN T22 D_CN(0) B14
DDC_DOUT_C0_DPP T23 D_CP(0) B16
DDC_DOUT_C1_DPN R20 D_CN(1) E15
DDC_DOUT_C1_DPP R21 D_CP(1) E17
DDC_DOUT_C2_DPN T19 D_CN(2) A17
DDC_DOUT_C2_DPP T20 D_CP(2) A15
DDC_DOUT_C3_DPN U21 D_CN(3) G21
DDC_DOUT_C3_DPP U22 D_CP(3) H20
DDC_DOUT_C4_DPN U20 D_CN(4) B20
DDC_DOUT_C4_DPP U19 D_CP(4) B22
DDC_DOUT_C5_DPN V23 D_CN(5) F20
DDC_DOUT_C5_DPP V24 D_CP(5) F22
DDC_DOUT_C6_DPN V22 D_CN(6) D22
DDC_DOUT_C6_DPP V21 D_CP(6) D20
DDC_DOUT_C7_DPN W19 D_CN(7) G23
DDC_DOUT_C7_DPP V19 D_CP(7) H22
DDC_DOUT_C8_DPN W23 D_CN(8) B26
DDC_DOUT_C8_DPP W24 D_CP(8) B28
DDC_DOUT_C9_DPN Y22 D_CN(9) F28
DDC_DOUT_C9_DPP Y23 D_CP(9) F26
DDC_DOUT_C10_DPN Y20 D_CN(10) C29
DDC_DOUT_C10_DPP Y21 D_CP(10) C27
DDC_DOUT_C11_DPN AA24 D_CN(11) G27
DDC_DOUT_C11_DPP AA23 D_CP(11) G29
DDC_DOUT_C12_DPN AA19 D_CN(12) D26
DDC_DOUT_C12_DPP AA20 D_CP(12) D28
DDC_DOUT_C13_DPN AC24 D_CN(13) H28
DDC_DOUT_C13_DPP AB24 D_CP(13) H26
DDC_DOUT_C14_DPN AC19 D_CN(14) E29
DDC_DOUT_C14_DPP AD19 D_CP(14) E27
DDC_DOUT_C15_DPN AC22 D_CN(15) J29
DDC_DOUT_C15_DPP AC23 D_CP(15) J27
DDC_DOUT_D0_DPN AB26 D_DN(0) AK14
DDC_DOUT_D0_DPP AC26 D_DP(0) AK16
DDC_DOUT_D1_DPN AA25 D_DN(1) AG15
DDC_DOUT_D1_DPP AB25 D_DP(1) AG17
DDC_DOUT_D2_DPN Y26 D_DN(2) AL17
DDC_DOUT_D2_DPP Y25 D_DP(2) AL15
DDC_DOUT_D3_DPN W26 D_DN(3) AE21
DDC_DOUT_D3_DPP W25 D_DP(3) AD20
DDC_DOUT_D4_DPN U26 D_DN(4) AK20
DDC_DOUT_D4_DPP V26 D_DP(4) AK22
DDC_DOUT_D5_DPN U25 D_DN(5) AF20
DDC_DOUT_D5_DPP U24 D_DP(5) AF22
DDC_DOUT_D6_DPN T25 D_DN(6) AH22
DDC_DOUT_D6_DPP T24 D_DP(6) AH20
DDC_DOUT_D7_DPN R26 D_DN(7) AE23
DDC_DOUT_D7_DPP R25 D_DP(7) AD22
DDC_DOUT_D8_DPN P24 D_DN(8) AK26
DDC_DOUT_D8_DPP P25 D_DP(8) AK28
DDC_DOUT_D9_DPN N24 D_DN(9) AF28
DDC_DOUT_D9_DPP M24 D_DP(9) AF26
DDC_DOUT_D10_DPN L25 D_DN(10) AJ29
DDC_DOUT_D10_DPP L24 D_DP(10) AJ27
DDC_DOUT_D11_DPN K26 D_DN(11) AE27
DDC_DOUT_D11_DPP K25 D_DP(11) AE29
DDC_DOUT_D12_DPN J26 D_DN(12) AH26
DDC_DOUT_D12_DPP J25 D_DP(12) AH28
DDC_DOUT_D13_DPN J24 D_DN(13) AD28
DDC_DOUT_D13_DPP H24 D_DP(13) AD26
DDC_DOUT_D14_DPN H26 D_DN(14) AG29
DDC_DOUT_D14_DPP G26 D_DP(14) AG27
DDC_DOUT_D15_DPN G25 D_DN(15) AC29
DDC_DOUT_D15_DPP G24 D_DP(15) AC27
DDC_SCTRL_AN R1 SCTRL_AN J3
DDC_SCTRL_AP P1 SCTRL_AP J5
DDC_SCTRL_BN AA3 SCTRL_BN AF4
DDC_SCTRL_BP AB4 SCTRL_BP AF2
DDC_SCTRL_CN W20 SCTRL_CN E23
DDC_SCTRL_CP W21 SCTRL_CP E21
DDC_SCTRL_DN N26 SCTRL_DN AG23
DDC_SCTRL_DP P26 SCTRL_DP AG21