8.3.2.1 Row Addressing

The DIN (input data), DCLKIN (input data clock), and DVALID (data valid) signals enable the DLPC410 to capture one row of customer input data and send that data to the DMD. For the DMD to know specifically to which row the data will be applied, the ROW_MD(1:0) (row mode), the ROW_AD(10:0) (row address), and the NS_FLIP (North/South Flip) signal inputs must be presented to the DLPC410 inputs during each row cycle. Table 11 shows the number of rows for each DMD supported by the DLPC410.

DMD data is loaded into the DMD SRAM pixels one row of data at a time. The DLP9500 and DLP9500UV require pattern data input to all four input data buses (A,B,C,D) while the DLP650LNIR, DLP7000 and DLP7000UV require pattern data to be input to two input data buses (A,B). The DLP650LNIR uses only the odd data bus pins of input buses A and B. The DMD input data buses are provided by the following DLPC410 outputs:

• DDC_DCLKOUT - high speed 2xLVDS data clock out to DMD
• SCTRL - high speed control bus to DMD
• DDC_DOUT[X:Y] - 2xLVDS data bus where X and Y depend on the DMD.

These signals are all output from the DLPC410 and are listed in Pin Configuration and Functions. Data and control from the DLPC410 are clocked into the DMD on both the rising and falling edges of the DDR data clocks: DDC_DCLKOUT_[A, B] for the 2 input bus DMDs and DDC_DCLKOUT_[A, B, C, D] for the 4 input bus DMDs. Data loading does not cause mirror state changes - mirrors transition to the next state only when a Mirror Clocking Pulse (Reset) operation is performed.

The row load length in clocks can be determined by the following equation: number row clocks = number of pixels per row / (total data buses bit width × 2 edges per clock). The "2 edges per clock" in the denominator is a direct result of the Dual Data Rate (DDR) nature of the DMD input data bus. This equation yields the results shown in Table 11

The DMD incorporates single row write operations using a row address counter that has different modes of operation. These modes are dependent on the state of the ROW_MD, ROW_AD, and NS_FLIP input signals. As shown in Table 12, ROW_MD(1:0) determines the row mode for a given Row Cycle, and, when ROW_MD = "10", then ROW_AD(10:0) selects the customer supplied single row address. ROW_MD and ROW_AD must be asserted and deasserted synchronously with DVALID and must be valid synchronous to the beginning of the data as shown in Figure 9. If only one specific mode will be utilized in a customer system application, it is certainly acceptable to leave these values at their same desired input levels for as long as desired.

Row address orientation depends on the North/South Flip Flag (NS_FLIP) input to the DLPC410. This input controls if the DMD starting row address starts at the top of the DMD (Row 0) and increments downward, or from the bottom of the DMD (last row) and decrements upward.

The row address counter does not automatically wrap-around when using the increment row address pointer instructions. For example, after the final row is addressed, the row address pointer must be set to row 0.