DLPS271 April   2024 DLPC7530

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Electrical Characteristics
    6. 5.6  Pin Electrical Characteristics
    7. 5.7  DMD HSSI Electrical Characteristics
    8. 5.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 5.9  V-by-One Interface Electrical Characteristics
    10. 5.10 FPD-Link LVDS Electrical Characteristics
    11. 5.11 USB Electrical Characteristics
    12. 5.12 System Oscillator Timing Requirements
    13. 5.13 Power Supply and Reset Timing Requirements
    14. 5.14 DMD HSSI Timing Requirements
    15. 5.15 DMD Low-Speed LVDS Timing Requirements
    16. 5.16 V-by-One Interface General Timing Requirements
    17. 5.17 FPD-Link Interface General Timing Requirements
    18. 5.18 Parallel Interface General Timing Requirements
    19. 5.19 Source Frame Timing Requirements
    20. 5.20 Synchronous Serial Port Interface Timing Requirements
    21. 5.21 Controller and Target I2C Interface Timing Requirements
    22. 5.22 Programmable Output Clock Timing Requirements
    23. 5.23 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    24. 5.24 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    25. 5.25 Multi-Trace ETM Interface Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Sources
      2. 6.3.2 Processing Delays
      3. 6.3.3 Parallel Interface
      4. 6.3.4 FPD-Link Interface
      5. 6.3.5 V-by-One Interface
      6. 6.3.6 DMD (HSSI) Interface
      7. 6.3.7 Program Memory Flash Interface
      8. 6.3.8 GPIO Supported Functionality
      9. 6.3.9 Debug Support
    4. 6.4 Device Operational Modes
      1. 6.4.1 Standby Mode
      2. 6.4.2 Active Mode
        1. 6.4.2.1 Normal Configuration
        2. 6.4.2.2 Low Latency Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
  9. 8 Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1  General Layout Guidelines
      2. 9.1.2  Power Supply Layout Guidelines
      3. 9.1.3  Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4  Layout Guideline for DLPC7530 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5  V-by-One Interface Layout Considerations
      6. 9.1.6  FPD-Link Interface Layout Considerations
      7. 9.1.7  USB Interface Layout Considerations
      8. 9.1.8  DMD Interface Layout Considerations
      9. 9.1.9  General Handling Guidelines for Unused CMOS-Type Pins
      10. 9.1.10 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
      1. 10.6.1 Video Timing Parameter Definitions
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     92

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

DLPC7530 ZDC Package676-Pin PBGATop ViewFigure 4-1 ZDC Package676-Pin PBGATop View
Table 4-1 Initialization, Board Level Test, and Debug
PINTYPE(1)DESCRIPTION
NAMENO.
POSENSEAE27I8Power-On Sense: Signal provided from external voltage monitoring circuit
('0' = All controller supply voltages not at valid level, '1' = All controller supply voltages have reached 90% specified minimum voltage)
Drive this signal to inactive (low) after the falling edge of PWRGOOD as specified. See Section 5.13 for specific timing requirements as well as the required power up and power down sequence.
This pin includes hysteresis.
PWRGOODAG30I8Power Good: Signal provided from external power supply of voltage monitor
A high value indicates all power is within operating voltage specifications and the system is safe to exit its reset state. A transition from high to low indicates that the controller or DMD supply voltage drops below its rated minimum level. This transition must occur prior to the supply voltage dropping per the timing specified, as this is an early warning of an imminent power loss condition.
This warning is required to enhance long term DMD reliability. When PWRGOOD goes low for the specified minimum time, a DMD park and full Controller reset are performed, protecting the DMD. Note that both controller and DMD supply voltages must be within operating voltage levels to successfully execute the DMD park. The minimum PWRGOOD deassertion time is used to protect the system input from glitches. When PWRGOOD is low, the Controller is held in its reset state.
See Section 5.13 for specific timing requirements as well as the required power up and power down sequence.
This pin includes hysteresis.
EXT_ARSTZAF29O8External Reset: General purpose reset output
('0' = Reset, '1' = Normal Operation)
This output is asserted low immediately upon POSENSE being asserted low, and remains low while POSENSE remains low. This signal remains low after POSENSE is set high, until released by software. This signal is also asserted low approximately 5µs after the detection of PWRGOOD going low, or any internally generated reset. In all cases, this signal remains active low for a minimum of 2ms.
Note: This signal can also be independently driven through the software register.
MTR_ARSTZAF27O8Color Wheel Motor Controller Reset: Color wheel motor controller reset output
('0' = Reset, '1' = Normal Operation)
This output is asserted low immediately upon POSENSE being asserted low, and remains low while POSENSE remains low. This signal remains low after POSENSE is set high, until released by software. This signal is also asserted low approximately 5µs after the detection of PWRGOOD going low, or any internally generated reset. In all cases, this signal remains active low for a minimum of 2ms.
Note: This signal can also be independently driven through the software register.

TCKAK19I8JTAG, ARM-ICE, and CPU MBIST Serial Data Clock.
This signal is shared between JTAG, ARM-ICE (TI test only), and CPU MBIST (Manufacturing test only) operation
Includes a weak internal pulldown
TMS1AH20I8JTAG Test Mode Select
Includes a weak internal pullup
TMS2AJ20I8ARM-ICE Test Mode Select
For normal operation, this pin must be left open or unconnected. Includes a weak internal pullup
TMS3AK20I8CPU MBIST Test Mode Select
For normal operation this pin must be left open or unconnected. Includes a weak internal pullup
TRSTZAG21I8JTAG, ARM-ICE, and CPU MBIST Reset.
This signal is shared between JTAG, ARM-ICE (TI test only), and CPU MBIST (Manufacturing test only) operation.
For normal operation, this pin must be pulled to ground through an external resistor with value 8kΩ or less. Failure to pull this pin low during normal operation causes start-up and initialization problems.
For JTAG Boundary Scan, ARM-ICE Debug operation, or CPU MBIST, this pin must be pulled-up or left disconnected. Includes a weak internal pullup and hysteresis
TDIAG20I8JTAG, ARM-ICE, and CPU MBIST: Serial Data In
Includes a weak internal pullup
TDO1AG19O8JTAG Serial Data Out
TDO2AH19O8ARM-ICE Serial Data Out
For normal operation, this pin must be left open or unconnected.
TDO3AJ19O8CPU MBIST Serial Data Out
For normal operation, this pin must be left open or unconnected.
ETM_TRACECLKC30O8TI internal use. Must be left unconnected (clock for trace debug)
ETM_TRACECTLD30O8TI internal use. Must be left unconnected (control for trace debug)
ICTSENK26I8IC Tristate Enable (Active high)
Asserting this signal transitions all outputs into tristate (except for the JTAG interface).
Includes a weak internal pulldown, however, an external pulldown is recommended for added protection. Also includes hysteresis
ICTSEM26I8TI internal use. Includes a weak internal pulldown, however, an external pulldown is recommended for added protection. Also includes hysteresis
TSTPT_0E29B8Test pin 0
This pin requires an external pulldown or pullup resistor (depending on the desired debug output as noted below) with a value of ≤ 10kΩ.
Tristated while PWRGOOD is asserted low. It may be driven as an output for debug use as described in Section 6.3.9.
TSTPT_1E30B8Test pin 1
This pin requires an external pulldown or pullup resistor (depending on the desired debug output as noted below) with a value of ≤ 10kΩ.
Tristated while PWRGOOD is asserted low. It may be driven as an output for debug use as described in Section 6.3.9.
TSTPT_2F26B8Test pin 2
This pin requires an external pulldown or pullup resistor (depending on the desired debug output as noted below) with a value of ≤ 10kΩ.
Tristated while PWRGOOD is asserted low. It can be driven as an output for debug use as described in Section 6.3.9.
TSTPT_3F27B8Test pin 3
This pin requires an external pulldown or pullup resistor (depending on the desired debug output as noted below) with a value of ≤ 10kΩ.
Tristated while PWRGOOD is asserted low. It may be driven as an output for debug use as described in Section 6.3.9.
TSTPT_4F28B8Test pin 4
This pin requires an external pulldown resistor (≤ 10kΩ).
Tristated while PWRGOOD is asserted low. It can be driven as an output for debug use as described in Section 6.3.9.
TSTPT_5F29B8Test pin 5
This pin requires an external pulldown resistor (≤ 10kΩ).
Tristated while PWRGOOD is asserted low. It can be driven as an output for debug use as described in Section 6.3.9.
TSTPT_6G26B8Test pin 6
This pin requires an external pulldown resistor (≤ 10kΩ).
Tristated while PWRGOOD is asserted low. It can be driven as an output for debug use as described in Section 6.3.9.
TSTPT_7G28B8Test pin 7
This pin requires an external pulldown resistor (≤ 10kΩ).
Tristated while PWRGOOD is asserted low. It can be driven as an output for debug use as described in Section 6.3.9.
HWTEST_ENL26I8Manufacturing test enable signal.
This signal must be connected directly to ground on the PCB for normal operation.
Includes a weak internal pulldown and hysteresis
(1) See Table 4-13 for more information on I/O definitions.
Table 4-2 Analog Front End
PINTYPE(1)DESCRIPTION
NAMENO.
AFE_ARSTZK2O8External reset: Provided for analog front end
('0' = Reset, '1' = normal operation)
This output is asserted low immediately upon POSENSE being asserted low, and remains low while POSENSE remains low. This signal remains low after POSENSE is set high, until released by software. This signal is also asserted low approximately 5µs after the detection of PWRGOOD going low, or any internally generated reset. In all cases, this signal remains active low for a minimum of 2ms.
Note: This signal can also be independently driven through the software register.
AFE_CLKK3O8External clock: Provides a fixed 5MHz clock for analog front end to support video decoder operation
AFE_IRQK4I8External interrupt: Provided to support analog front end
('0' = No Interrupt, '1' = Interrupt)
Includes a weak internal pulldown and hysteresis
ALF_VSYNCK5I8Dedicated VSYNC: Provided to support analog front end autolock functionality
Includes a weak internal pulldown and hysteresis
ALF_HSYNCJ1I8Dedicated HSYNC: Provided to support analog front end autolock functionality
Includes weak internal pulldown and hysteresis
ALF_CSYNCJ2I8Dedicated composite sync (sync on green): Provided to support analog front end autolock functionality
Includes weak internal pulldown and hysteresis.
(1) See Table 4-13 for more information on I/O definitions.
Table 4-3 V-by-One® Interface Input Data and Control
PINTYPE(1)DESCRIPTION(2)(3)
NAMENO.
VX1_DATA0_P
VX1_DATA0_N
VX1_DATA1_P
VX1_DATA1_N
VX1_DATA2_P
VX1_DATA2_N
VX1_DATA3_P
VX1_DATA3_N
VX1_DATA4_P
VX1_DATA4_N
VX1_DATA5_P
VX1_DATA5_N
VX1_DATA6_P
VX1_DATA6_N
VX1_DATA7_P
VX1_DATA7_N		C18
D18
A19
B19
C20
D20
A21
B21
C22
D22
A23
B23
C24
D24
A25
B25		I1V-by-One interface data lanes
VX1_HTPDNE17O4V-by-One interface hot plug detect (controller receiver pulls this signal low to indicate its presence to the transmitter)
This signal is open drain at the controller output. A pullup resistor is required at the transmitter.
VX1_LOCKNE19O4V-by-One interface clock detect lock (controller receiver pulls this signal low to indicate clock extraction lock to the transmitter)
This signal is open drain at the controller output. A pullup resistor is required at the transmitter.
VX1_CM_CKREF0
VX1_CM_CKREF1
VX1_CM_CKREF2
VX1_CM_CKREF3		E20
E21
E23
E24		I1V-by-One reserved: Tie these reserved pins to ground.
VX1_CM_AMOUT0
VX1_CM_AMOUT1
VX1_CM_AMOUT2
VX1_CM_AMOUT3		F19
F21
F22
F23		O1V-by-One reserved: These pins are reserved and must remain unconnected.
(1) See Table 4-13 for more information on I/O definitions.
(2) The system supports 1-lane, 2-lane, 4-lane, or 8-lane operation, based on the bandwidth requirement of the input source. The inputs for any unused data lanes must be left open.
(3) The V-by-One port supports limited lane remapping to help optimize board layout. The details are described in Section 6.3.5.
Table 4-4 OpenLDI (FPD-Link I) Ports Input Data and Control
PINTYPE(1)DESCRIPTION(2)(3)
NAMENO.
FPDA_CLK_P
FPDA_CLK_N		H3
H4		I5FPD-Link Port A Clock Lane
FPDA_DATAA_P
FPDA_DATAA_N
FPDA_DATAB_P
FPDA_DATAB_N
FPDA_DATAC_P
FPDA_DATAC_N
FPDA_DATAD_P
FPDA_DATAD_N
FPDA_DATAE_P
FPDA_DATAE_N		G1
G2
F3
F4
E1
E2
D3
D4
C1
C2		I5FPD-Link Port A Data Lanes
FPDB_CLK_P
FPDB_CLK_N		A4
B4		I5FPD-Link Port B Clock Lane
FPDB_DATAA_P
FPDB_DATAA_N
FPDB_DATAB_P
FPDB_DATAB_N
FPDB_DATAC_P
FPDB_DATAC_N
FPDB_DATAD_P
FPDB_DATAD_N
FPDB_DATAE_P
FPDB_DATAE_N		C5
D5
A6
B6
C7
D7
A8
B8
C9
D9		I5FPD-Link Port B Data Lanes
FPDC_CLK_P
FPDC_CLK_N		A10
B10		I5FPD-Link Port C—Reserved for Parallel Port use only.
FPDC_DATAA_P
FPDC_DATAA_N
FPDC_DATAB_P
FPDC_DATAB_N
FPDC_DATAC_P
FPDC_DATAC_N
FPDC_DATAD_P
FPDC_DATAD_N
FPDC_DATAE_P
FPDC_DATAE_N		C11
D11
A12
B12
C13
D13
A14
B14
C15
D15		I5FPD-Link Port C Data Lanes—Reserved for Parallel Port use only.
(1) See Table 4-13 for more information on I/O definitions.
(2) Throughout this document the terms FPD and FPD-Link refer to OpenLDI (FPD-Link I).
(3) Tie the inputs for any unused port(s) to ground, or pull to ground through an external resistor.
Table 4-5 Parallel Port Input Data and Control
PINTYPE(1)DESCRIPTION
PARALLEL RGB MODE
NAMENO.
PCLK (FPDB_DATAB_N)B6I6Pixel clock
VSYNC (FPDA_DATAE_P)C1I6Vsync
HSYNC (FPDA_DATAE_N)C2I6Hsync
DATEN (FPDB_DATAE_N)D9I6Data Valid(2)
FIELD (FPDC_DATAE_P)C15I6Field—This can be used as the 2-D field signal for interlaced sources as well as the 3-D TOPFIELD signal for decimated frame sequential 3-D sources.
3D_REF (FPDC_DATAE_N)D15I63D Left/Right Reference
(RGB 10,10,10)
PDATA_A0 (FPDA_CLK_P)
PDATA_A1 (FPDA_CLK_N)
PDATA_A2 (FPDA_DATAA_P)
PDATA_A3 (FPDA_DATAA_N)
PDATA_A4 (FPDA_DATAB_P)
PDATA_A5 (FPDA_DATAB_N)
PDATA_A6 (FPDA_DATAC_P)
PDATA_A7 (FPDA_DATAC_N)
PDATA_A8 (FPDA_DATAD_P)
PDATA_A9 (FPDA_DATAD_N)		H3
H4
G1
G2
F3
F4
E1
E2
D3
D4		I6Channel A Data (bit weight 0.25)
Channel A Data (bit weight 0.5)
Channel A Data (bit weight 1)
Channel A Data (bit weight 2)
Channel A Data (bit weight 4)
Channel A Data (bit weight 8)
Channel A Data (bit weight 16)
Channel A Data (bit weight 32)
Channel A Data (bit weight 64)
Channel A Data (bit weight 128)
(RGB 10,10,10)
PDATA_B0 (FPDB_CLK_P)
PDATA_B1 (FPDB_CLK_N)
PDATA_B2 (FPDB_DATAA_P)
PDATA_B3 (FPDB_DATAA_N)
PDATA_B4 (FPDB_DATAB_P)
PDATA_B5 (FPDB_DATAC_P)
PDATA_B6 (FPDB_DATAC_N)
PDATA_B7 (FPDB_DATAD_P)
PDATA_B8 (FPDB_DATAD_N)
PDATA_B9 (FPDB_DATAE_P)		A4
B4
C5
D5
A6
C7
D7
A8
B8
C9		I6Channel B Data (bit weight 0.25)
Channel B Data (bit weight 0.5)
Channel B Data (bit weight 1)
Channel B Data (bit weight 2)
Channel B Data (bit weight 4)
Channel B Data (bit weight 8)
Channel B Data (bit weight 16)
Channel B Data (bit weight 32)
Channel B Data (bit weight 64)
Channel B Data (bit weight 128)
(RGB 10,10,10)
PDATA_C0 (FPDC_CLK_P)
PDATA_C1 (FPDC_CLK_N)
PDATA_C2 (FPDC_DATAA_P)
PDATA_C3 (FPDC_DATAA_N)
PDATA_C4 (FPDC_DATAB_P)
PDATA_C5 (FPDC_DATAB_N)
PDATA_C6 (FPDC_DATAC_P)
PDATA_C7 (FPDC_DATAC_N)
PDATA_C8 (FPDC_DATAD_P)
PDATA_C9 (FPDC_DATAD_N)		A10
B10
C11
D11
A12
B12
C13
D13
A14
B14		I6Channel C Data (bit weight 0.25)
Channel C Data (bit weight 0.5)
Channel C Data (bit weight 1)
Channel C Data (bit weight 2)
Channel C Data (bit weight 4)
Channel C Data (bit weight 8)
Channel C Data (bit weight 16)
Channel C Data (bit weight 32)
Channel C Data (bit weight 64)
Channel C Data (bit weight 128)
(1) See Table 4-13 for more information on I/O definitions.
(2) If the DATEN is not actively driven, then it must be pulled up to 3.3V with a weak pullup resistor (50kΩ max).
Table 4-6 DMD Reset and Low Speed Interfaces
PINTYPE(1)DESCRIPTION
NAMENO.
DMD_LS0_CLK_P
DMD_LS0_CLK_N		AH17
AG17		O2DMD low speed differential interface, Port 0 Clock
DMD_LS0_WDATA_P
DMD_LS0_WDATA_N		AK16
AJ16		O2DMD low speed differential interface, Port 0 Write Data
DMD_LS1_CLK_P
DMD_LS1_CLK_N		AH15
AG15		O2DMD low speed differential interface, Port 1 Clock (2)
DMD_LS1_WDATA_P
DMD_LS1_WDATA_N		AK14
AJ14		O2DMD low speed differential interface, Port 1Write Data (2)
DMD_LS0_RDATAAH13I3DMD, low speed single ended serial interface, Port 0 Read Data (3)
DMD_LS1_RDATAAG13I3DMD, low speed single ended serial interface, Port 1 Read Data (2)(3). If this port is not used, this signal requires an external pullup or pulldown to keep this input from floating.
DMD_DEN_ARSTZAK12O3DMD driver enable signal or Active Low Asynchronous Reset
('1' = Enabled, '0' = Reset)
This signal is driven low after the DMD is parked and before power is removed from the DMD.
If the 1.8V power to the DLPC7530 is independent of the 1.8V power to the DMD, then an external pulldown resistor must be used to hold the signal low in the event the DLPC7530 power is inactive while DMD power is applied.
(1) See Table 4-13 for more information on I/O definitions.
(2) DMD LS1 port is reserved for single controller, two DMD applications.
(3) All control interface reads make use of the single ended low speed signals. The read data is clocked by the low speed differential write clock.
Table 4-7 DMD HSSI (High Speed Serial Interface)
PIN (1)TYPE(2)DESCRIPTION
NAMENO.
DMD_HSSI0_CLK_P
DMD_HSSI0_CLK_N		AK25
AJ25		O7DMD high speed serial interface, Port 0 Clock Lane
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N		AK29
AJ29
AH28
AG28
AK27
AJ27
AH26
AG26
AH24
AG24
AK23
AJ23
AH22
AG22
AK21
AJ21		O7DMD high speed serial interface, Port 0 Data Lanes
DMD_HSSI1_CLK_P
DMD_HSSI1_CLK_N		AH7
AG7		O7DMD high speed serial interface, Port 1 Clock Lane
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N		AH11
AG11
AK10
AJ10
AH9
AG9
AK8
AJ8
AK6
AJ6
AH5
AG5
AK4
AJ4
AK2
AJ2		O7DMD high speed serial interface, Port 1 Data Lanes
HSSI_ATETESTAJ12O7Manufacturing Test use only—Must be left open (that is, unconnected)
(1) A number of pin remapping options are available for the HSSI high speed channels to aid with optimizing board signal routing. See Section 6.3.6 for information on these pin remapping options.
(2) See Table 4-13 for more information on I/O definitions.
Table 4-8 Program Memory (FLASH) Interface
PINTYPE(1)DESCRIPTION
NAMENO.
PM_CSZ_0T27O8Chip select: boot FLASH only (Boot FLASH must use this chip select.)
PM_CSZ_1T28O8Chip select:
PM_CSZ_2T29O8Chip select: additional peripheral device
PM_ADDR_0T30O8Address bit (LSB)
PM_ADDR_1U26O8Address bit
PM_ADDR_2U27O8Address bit
PM_ADDR_3U29O8Address bit
PM_ADDR_4U30O8Address bit
PM_ADDR_5V29O8Address bit
PM_ADDR_6V28O8Address bit
PM_ADDR_7V27O8Address bit
PM_ADDR_8V26O8Address bit
PM_ADDR_9W30O8Address bit
PM_ADDR_10W29O8Address bit
PM_ADDR_11W28O8Address bit
PM_ADDR_12W26O8Address bit
PM_ADDR_13Y30O8Address bit
PM_ADDR_14Y29O8Address bit
PM_ADDR_15Y28O8Address bit
PM_ADDR_16Y27O8Address bit
PM_ADDR_17Y26O8Address bit
PM_ADDR_18AA30O8Address bit
PM_ADDR_19AA29O8Address bit
PM_ADDR_20AA27O8Address bit
PM_ADDR_21AA26O8Address bit
PM_ADDR_22AB29O8Address bit
PM_ADDR_23 (GPIO_47)AB28B8Address bit (MSB)(2)
PM_WEZR28O8Write enable (active low)
PM_OEZR29O8Output enable (active low)
PM_BLSZ_0R30O8Lower Byte (7:0) Enable (active low)—only applicable to devices using PM_CSZ_1 or PM_CSZ_2
PM_BLSZ_1T26O8Upper Byte (15:8) Enable (active low)—only applicable to devices using PM_CSZ_1 or PM_CSZ_2
PM_Data_0L29B8Data bit
PM_Data_1L30B8Data bit
PM_Data_2L28B8Data bit
PM_Data_3M27B8Data bit
PM_Data_4M28B8Data bit
PM_Data_5M29B8Data bit
PM_Data_6M30B8Data bit
PM_Data_7N26B8Data bit
PM_Data_8N27B8Data bit
PM_Data_9N29B8Data bit
PM_Data_10N30B8Data bit
PM_Data_11P26B8Data bit
PM_Data_12P27B8Data bit
PM_Data_13P28B8Data bit
PM_Data_14P29B8Data bit
PM_Data_15R26B8Data bit
(1) See Table 4-13 for more information on I/O definitions.
(2) The Program Memory address bus can be extended by one bit to 24 bits by making use of GPIO_47. Add an external pulldown resistor when this GPIO is configured for this purpose.
Table 4-9 Peripheral Interfaces
PINTYPE(1)DESCRIPTION
NAMENO.
IIC0_SCLE27B13I2C Port 0 (controller-target). Typically, target for host command and control to controller, SCL (bidirectional, open-drain): An external pullup is required. The minimum acceptable value for this pullup is 1KΩ.
IIC0_SDAD29B13I2C Port 0 (controller-target). Typically, target for Host Command and Control to Controller, SDA. (bidirectional, open-drain): An external pullup is required. The minimum acceptable value for this pullup is 1KΩ.
SSP0_TXDAD27O8SSP/SPI Port 0 Data Out (controller): transmit data pin
SSP0_RXDAD29I8SSP/SPI Port 0 Data In (controller): receive data pin
SSP0_CLKAD28O8SSP/SPI Port 0 clock (controller): clock pin
SSP0_CSZ_2AC28O8SPI Port 0 chip select 2 (controller): chip select (active low)
An external pullup resistor (≤ 100kΩ) is suggested to avoid a floating chip select input to the external device.
SSP0_CSZ_1AC26O8SPI Port 0 chip select 1 (controller): chip select (active low)
An external pullup resistor (≤ 100kΩ) is suggested to avoid a floating chip select input to the external device.
SSP0_CSZ_0AB27O8SPI Port 0 chip select 0 (controller): chip select (active low)
An external pullup resistor (≤ 100kΩ) is suggested to avoid a floating chip select input to the external device.
UART0_TXDP4O8UART Port 0 (peripheral): serial data transmit
This UART port is reserved for TI debug. An external pullup resistor (≤ 10kΩ) is required.
UART0_RXDP5I8UART Port 0 (peripheral): serial data receive
This UART port is reserved for TI debug. An external pullup resistor (≤ 10kΩ) is required.
UART0_RTSZN2O8UART Port 0 (peripheral): ready to send (hardware flow control signal [active low])
This UART port is reserved for TI debug. An external pullup resistor (≤ 10kΩ) is required.
UART0_CTSZN3I8UART Port 0 (peripheral): clear to send (hardware flow control signal [active low])
This UART port is reserved for TI debug. An external pullup resistor (≤ 10kΩ) is required.
USB_DAT_P
USB_DAT_N		B27
A27		B11USB OTG Data Lane (controller-peripheral)
USB_VBUSD26B11USB OTG 5V Power Supply Detection (controller-peripheral)
USB_IDC27IOtherUSB OTG Mini Receptacle Identification (controller-peripheral)
USB_TXRTUNEC26BGNDUSB OTG Reference Resistor
An external reference resistor must be connected as shown in Section 9.1.7.
USB_XIA29IGNDUSB OTG External Oscillator XI—Not used (clock provided internally)
For normal operation this pin must be connected to GND.
USB_XOB29BGNDUSB OTG External Oscillator XO—Not used (clock provided internally)
For normal operation this pin must be left open (unconnected).
USB_ANALOGTESTC28BOtherUSB OTG Manufacturing Test
This pin must be left open (unconnected).
PMD_INTZAD26I8Interrupt from DLPA100 (active low)
This signal requires an external pullup. It also has hysteresis.
CW_PWMAE30O8Color wheel control PWM
CW_INDEXAE29I8Color wheel index
 This pin has hysteresis.
(1) See Table 4-13 for more information on I/O definitions.
Table 4-10 GPIO Peripheral Interface
PINTYPE(1)DESCRIPTION(2)(3)(4)
NAMENO.
GPIO_87K1B8General purpose I/O 87: Options:
  1. Alt 0: Reserved
  2. Alt 1: DAO_CLKIN (I)
  3. Optional GPIO
GPIO_86L5B8General purpose I/O 86: Options:
  1. Alt 0: Reserved
  2. Alt 1: DAO_DI_1 (I)
  3. Optional GPIO
GPIO_85L4B8General purpose I/O 85: Options:
  1. Alt 0: Reserved
  2. Alt 1: DAO_DI_0 (I)
  3. Optional GPIO
GPIO_84L3B8General purpose I/O 84: Options:
  1. Alt 0: Reserved
  2. Alt 1: HBT_CLKIN_2 (I)
  3. Optional GPIO
GPIO_83L2B8General purpose I/O 83: Options:
  1. Alt 0: Reserved
  2. Alt 1: HBT_DI_2 (I)
  3. Optional GPIO
GPIO_82M5B8General purpose I/O 82: Options:
  1. Alt 0: Reserved
  2. Alt 1: HBT_CLKIN_1 (I)
  3. Optional GPIO
GPIO_81M4B8General purpose I/O 81: Options:
  1. Alt 0: Reserved
  2. Alt 1: HBT_DI_1 (I)
  3. Optional GPIO
GPIO_80M2B8General purpose I/O 80: Options:
  1. Alt 0: Reserved
  2. Alt 1: HBT_CLKIN_0 (I)
  3. Optional GPIO
GPIO_79M1B8General purpose I/O 79: Options:
  1. Alt 0: Reserved
  2. Alt 1: HBT_DI_0 (I)
  3. Optional GPIO
GPIO_78N5B8General purpose I/O 78: Options:
  1. Alt 0: Reserved
  2. Alt 1: SEQ_SYNC (B/ open drain)
  3. Optional GPIO
GPIO_77N4B8General purpose I/O 77: Options:
  1. Alt 0: Reserved
  2. Alt 1: EFSYNC (O)/ DASYNC (I)
  3. Optional GPIO
GPIO_76AD5B8General purpose I/O 76: Options:
  1. Alt 0: AWC1_DACD_PWMB_1 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_75AC1B8General purpose I/O 75: Options:
  1. Alt 0: AWC1_DACS_PWMA_1 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_74AC2B8General purpose I/O 74: Options:
  1. Alt 0: AWC1_DACD_PWMB_0 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_73AC4B8General purpose I/O 73: Options:
  1. Alt 0: AWC1_DACS_PWMA_0 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_72AC5B8General purpose I/O 72: Options:
  1. Alt 0: AWC1_DACCLK_0_1 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_71AD1B8General purpose I/O 71: Options:
  1. Alt 0: AWC1_OUT_ENZ (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_70AD2B8General purpose I/O 70: Options:
  1. Alt 0: AWC0_DACD_PWMB_1 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_69AD3B8General purpose I/O 69: Options:
  1. Alt 0: AWC0_DACS_PWMA_1 (O)
  2. Alt 1: MEMAUX_1 (O) (#2)
  3. Optional GPIO
GPIO_68AD4B8General purpose I/O 68: Options:
  1. Alt 0: AWC0_DACD_PWMB_0 (O)
  2. Alt 1: IIC2_SDA (B) (#3)
  3. Optional GPIO
GPIO_67AF4B8General purpose I/O 67: Options:
  1. Alt 0: AWC0_DACS_PWMA_0 (O)
  2. Alt 1: IIC2_SCL (B) (#3)
  3. Optional GPIO
GPIO_66AE2B8General purpose I/O 66: Options:
  1. Alt 0: AWC0_DACCLK_0_1 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_65AE3B8General purpose I/O 65: Options:
  1. Alt 0: AWC0_OUT_ENZ (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_64AE4B8General purpose I/O 64: Options:
  1. Alt 0: OCLKB (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_63AG2B8General purpose I/O 63: Options:
  1. Alt 0: PWM_OUT_UVLED (O)
  2. Alt 1: OCLKD (O) (#2)
  3. Optional GPIO
GPIO_62AG3B8General purpose I/O 62: Options:
  1. Alt 0: PWM_OUT_IRLED (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_61AF1B8General purpose I/O 61: Options:
  1. Alt 0: PWM_OUT_BLED (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_60AF2B8General purpose I/O 60: Options:
  1. Alt 0: PWM_OUT_GLED (O)
  2. Alt 1: UART2_RXD (I) (#2)
  3. Optional GPIO
GPIO_59AG1B8General purpose I/O 59: Options:
  1. Alt 0: PWM_OUT_RLED (O)
  2. Alt 1: UART2_TXD (O) (#2)
  3. Optional GPIO
GPIO_58V1B8General purpose I/O 58: Options:
  1. Alt 0: PWM_OUT_STD_2 (O)
  2. Alt 1: ALF_COAST (O)
  3. Optional GPIO
GPIO_57V2B8General purpose I/O 57: Options:
  1. Alt 0: PWM_OUT_STD_1 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_56W2B8General purpose I/O 56: Options:
  1. Alt 0: PWM_OUT_STD_0 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_55K29B8General purpose I/O 55: Options:
  1. Alt 0: PWM_OUT_CW2 (O)
  2. Alt 1:
  3. Optional GPIO
GPIO_54K28B8General purpose I/O 54: Options:
  1. Alt 0: PWM_OUT_CW1 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_53W3B8General purpose I/O 53: Options:
  1. Alt 0: Reserved
  2. Alt 1: LED_DRIVER_ON (O)
  3. Optional GPIO
GPIO_52W4B8General purpose I/O 52: Options:
  1. Alt 0: Reserved
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_51V5B8General purpose I/O 51: Options:
  1. Alt 0: Reserved
  2. Alt 1: DMD_PWR_EN (O)
  3. Optional GPIO
GPIO_50AC29B8General purpose I/O 50: Options:
  1. Alt 0: SSP0_CSZ_3 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_49AC30B8General purpose I/O 49: Options:
  1. Alt 0: SSP0_CSZ_4 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_48AB26B8General purpose I/O 48: Options:
  1. Alt 0: USB OTG External USB Switch Control (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_47AB28B8General purpose I/O 47: Options:
  1. Alt 0: PM_ADDR_23 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_46K27B8General purpose I/O 46: Options:
  1. Alt 0: CW_Index_2 (I) (#1)
  2. Alt 1: SSP2_BC_CSZ (O-MST/I-SLV)
  3. Optional GPIO
GPIO_45J30B8General purpose I/O 45: Options:
  1. Alt 0: CW_Index_1 (I) (#1)
  2. Alt 1: SSP2_CSZ_2 (O-MST/I-SLV)
  3. Optional GPIO
GPIO_44J29B8General purpose I/O 44: Options:
  1. Alt 0: OCLKC (O) (#1)
  2. Alt 1: SSP2_CSZ_1 (O-MST/I-SLV)
  3. Optional GPIO
GPIO_43J27B8General purpose I/O 43: Options:
  1. Alt 0: OCLKD (O) (#1)
  2. Alt 1: SSP2_CSZ_0 (O-MST/I-SLV)
  3. Optional GPIO
GPIO_42J26B8General purpose I/O 42: Options:
  1. Alt 0: IIC2_SDA (B) (#1)
  2. Alt 1: SSP2_DO (O)
  3. Optional GPIO
GPIO_41H30B8General purpose I/O 41: Options:
  1. Alt 0: IIC2_SCL (B) (#1)
  2. Alt 1: SSP2_DI (I)
  3. Optional GPIO
GPIO_40H29B8General purpose I/O 40: Options:
  1. Alt 0: MEMAUX_1 (O) (#1)
  2. Alt 1: SSP2_SCLK (O-MST/I-SLV)
  3. Optional GPIO
GPIO_39H28B8General purpose I/O 39: Options:
  1. Alt 0: UART2_RXD (I) (#1)
  2. Alt 1: HBT_CLKOUT (O)
  3. Optional GPIO
GPIO_38H27B8General purpose I/O 38: Options:
  1. Alt 0: UART2_TXD (O) (#1)
  2. Alt 1: HBT_DO (O)
  3. Optional GPIO
GPIO_37H26B8General purpose I/O 37: Options:
  1. Alt 0: CW_Index_2 (I) (#2)
  2. Alt 1: DAO_CLKOUT (O)
  3. Optional GPIO
GPIO_36G30B8General purpose I/O 36: Options:
  1. Alt 0: CW_Index_1 (I) (#2)
  2. Alt 1: DAO_DO_1 (O)
  3. Optional GPIO
GPIO_35G29B8General purpose I/O 35: Options:
  1. Alt 0: OCLKC (O) (#2)
  2. Alt 1: DAO_DO_0 (O)
  3. Optional GPIO
GPIO_34Y1B8General purpose I/O 34: Options:
  1. Alt 0: WRP_CAMERA_TRIG (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_33Y2B8General purpose I/O 33: Options:
  1. Alt 0: PAUX11 (O) {CW Spoke}
  2. Alt 1: IIC2_SDA (B) (#2)
  3. Optional GPIO
GPIO_32Y4B8General purpose I/O 32: Options:
  1. Alt 0: PAUX10 (O) {CW Rev}
  2. Alt 1: IIC2_SCL (B) (#2)
  3. Optional GPIO
GPIO_31Y5B8General purpose I/O 31: Options:
  1. Alt 0: PAUX9 (O) {XPR-Y}
  2. Alt 1: PAUX_INT3 (O)
  3. Optional GPIO
GPIO_30AA1B8General purpose I/O 30: Options:
  1. Alt 0: PAUX8 (O) {XPR-X}
  2. Alt 1: PAUX_INT2 (O)
  3. Optional GPIO
GPIO_29AA2B8General purpose I/O 29: Options:
  1. Alt 0: PAUX7 (O) {SSI Subframe}
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_28AA3B8General purpose I/O 28: Options:
  1. Alt 0: PAUX6 (O) {UV_LED_EN}
  2. Alt 1: LEDSEL_4 (O)
  3. Optional GPIO
GPIO_27AA4B8General purpose I/O 27: Options:
  1. Alt 0: PAUX5 (O) {IR_LED_EN}
  2. Alt 1: LEDSEL_3 (O)
  3. Optional GPIO
GPIO_26AA5B8General purpose I/O 26: Options:
  1. Alt 0: PAUX4 (O) {B_LED_EN}
  2. Alt 1: LEDSEL_2 (O)
  3. Optional GPIO
GPIO_25AB2B8General purpose I/O 25: Options:
  1. Alt 0: PAUX3 (O) {G_LED_EN}
  2. Alt 1: LEDSEL_1 (O)
  3. Optional GPIO
GPIO_24AB3B8General purpose I/O 24: Options:
  1. Alt 0: PAUX2 (O) {R_LED_EN}
  2. Alt 1: LEDSEL_0 (O)
  3. Optional GPIO
GPIO_23AB4B8General purpose I/O 23: Options:
  1. Alt 0: PAUX1 (O) {SEQ Index}
  2. Alt 1: PAUX_INT1 (O)
  3. Optional GPIO
GPIO_22AB5B8General purpose I/O 22: Options:
  1. Alt 0: PAUX0 (O) {LED SENSE}
  2. Alt 1: PAUX_INT0 (O)
  3. Optional GPIO
GPIO_21P3B8General purpose I/O 21: Options:
  1. Alt 0: PWM-IN1 (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_20P2B8General purpose I/O 20: Options:
  1. Alt 0: PWM-IN0 (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_19P1B8General purpose I/O 19: Options:
  1. Alt 0: IR1 (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_18R5B8General purpose I/O 18: Options:
  1. Alt 0: IR0 (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_17R4B8General purpose I/O 17: Options:
  1. Alt 0: N/A
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_16R2B8General purpose I/O 16: Options:
  1. Alt 0: UART1_RTSZ (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_15R1B8General purpose I/O 15: Options:
  1. Alt 0: UART1_CTSZ (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_14T3B8General purpose I/O 14: Options:
  1. Alt 0: UART1_RXD (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_13T4B8General purpose I/O 13: Options:
  1. Alt 0: UART1_TXD (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_12T5B8General purpose I/O 12: Options:
  1. Alt 0: IIC1_SDA (B)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_11T2B8General purpose I/O 11: Options:
  1. Alt 0: IIC1_SCL (B)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_10V3B8General purpose I/O 10: Options:
  1. Alt 0: SAS_INTGTR_EN (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_09U1B8General purpose I/O 09: Options:
  1. Alt 0: SAS_CSZ (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_08U2B8General purpose I/O 08: Options:
  1. Alt 0: SAS_DO (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_07U4B8General purpose I/O 07: Options:
  1. Alt 0: SAS_DI (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_06V4B8General purpose I/O 06: Options:
  1. Alt 0: SAS_CLK (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_05A17B8General purpose I/O 05: Options:
  1. Alt 0: SSP1_CSZ_2 (O-MST/I-SLV)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_04B17B8General purpose I/O 04: Options:
  1. Alt 0: SSP1_CSZ_1 (O-MST/I-SLV)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_03B15B8General purpose I/O 03: Options:
  1. Alt 0: SSP1_CSZ_0 (O-MST/I-SLV)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_02C16B8General purpose I/O 02: Options:
  1. Alt 0: SSP1_DO (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_01D16B8General purpose I/O 01: Options:
  1. Alt 0: SSP1_DI (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_00E16B8General purpose I/O 00: Options:
  1. Alt 0: SSP1_SCLK (O-MST/I-SLV)
  2. Alt 1: N/A
  3. Optional GPIO
(1) See Table 4-13 for more information on I/O definitions.
(2) This table defines the GPIO capabilities of the DLPC7530. Please see Section 6.3.8 for specific product configuration allocations of these GPIO.
(3) Most GPIO have at least one alternate hardware functional use in addition to being available as a general purpose I/O. Depending on the product configuration, GPIO may be reserved specifically for use as an alternate hardware function (and would therefore not be available as a general purpose I/O). More information on GPIO allocations for specific product configurations can be found in Section 6.3.8.
(4) All GPIO that are available as a general purpose I/O must be configured as an input, a standard output, or an open-drain output. This is set in the flash configuration. Configure unused GPIO as a logic zero output and leave unconnected, otherwise an external pullup or pulldown resistor is required to avoid a floating input. The reset default for all GPIO is as an input signal.
An external pullup resistor (≤ 10kΩ) is required for each signal configured as open-drain output.
Table 4-11 Clock and Support
PINTYPE(1)DESCRIPTION
NAMENO.
REFCLKA_IAJ18I9Crystal A Input: Reference clock crystal input(2)(3)
REFCLKA_OAK18O10Crystal A Output: Reference clock crystal output(2)
REFCLKB_IB16I14Crystal B Input: Reference clock crystal input(2)(3)
REFCLKB_OA16O15Crystal B Output: Reference clock crystal output(2)
OCLKAAD30O8General Purpose Output Clock A (4)
Targeted for driving Color Wheel motor controller. Frequency is software programmable, with a power-up default frequency of 0.77MHz.
Note: The output frequency is not affected by non-power-up reset operations (that is, the system holds the last programmed value until system is power cycled).
(1) See Table 4-13 for more information on I/O definitions.
(2) For more information on this signal see Section 5.12.
(3) For applications where an external oscillator is used in place of a crystal, use an oscillator to drive this pin.
(4) For more information on this signal see Section 5.22.
Table 4-12 Power and Ground
PINTYPE(1)DESCRIPTION
NAMENO.
VDD115_PLLMAAE18PWR1.15V digital power for MCG (Controller Clock Generator A) PLL
VDD115_PLLMBF15PWR1.15V digital power for MCG (Controller Clock Generator B) PLL
VAD115_PLLSF16PWR1.15V analog power for SCG doubler PLL
VAD18_PLLMAAE19PWR1.8V analog power for MCG (Controller Clock Generator A) PLL
VAD18_PLLMBF14PWR1.8V analog power for MCG (Controller Clock Generator B) PLL
VAD33_OSCAY18PWR3.3V analog power for Crystal-OSC
VAD33_OSCBL17PWR3.3V analog power for Crystal-OSC
VAD115_FPDF7,F9,F11,J6,L12PWR1.15V analog power for FPD
VDD33_FPDE6,E8,E10,E12,E14,G6,L11,L13PWR3.3V digital power for FPD
VAD115_VX1F24,L18PWR1.15V analog power for VX1
VAD18_VX1E18,L19PWR1.8V analog power for VX1
VAD33_USBD27,E26,F25PWR3.3V analog power for USB
VDD18_SCSL16,R6,T25,AE16PWR1.8V digital power for SCS DRAM
VDD121_SCSL15,N11,P20,U11,V20,Y16PWR1.21-V digital power for SCS SRAM
VAD115_HSSIY14,Y19,AF7,AF9,AF11,AF13AF21,AF23,AF25PWR1.15V analog power for HSSI interface
VAD115_HSSI0_PLLAE22PWR1.15V analog power for HSSI-0 PLL
VAD115_HSSI1_PLLAE10PWR1.15V analog power for HSSI-1 PLL
VDD33_HSSIY12,Y20,AE8,AE12,AE20,AE24PWR3.3V digital power for HSSI interface
VAD18_LSIFY15,AE13,AE14PWR1.8V analog power for DMD low-speed interface
LVDS_VREFTESTAF16Manufacturing test use only; must be left open-unconnected
VDD115L14,L20,M11,N20,P11,R20,T11,U20,V11,W20,Y11,Y13,Y17PWR1.15V core power
VDD33H25,K25,L6,M20,M25,N6,P25,R11,T20,U6,V25,W6,W11,Y25,AA6,AB25,AC6,AD25,AE6PWR3.3V digital power
VSSA1,A2,A3,A5,A7,A9,A11,A13,A15,A18,A20,A22,A24,A26,A28,A30,B1,B2,B3,B5,B7,B9,B11,B13,B18,B20,B22,B24,B26,B28,B30,C3,C4,C6,C8,C10,C12,C14,C17,C19,C21,C23,C25,C29,D1,D2,D6,D8,D10,D12,D14,D17,D19,D21,D23,D25,D28,E3,E4,E5,E7,E9,E11,E13,E15,E22,E25,E28,F1,F2,F5,F6,F8,F10,F12,F13,F17,F18,F20,F30,G3,G4,G5,G27,H1,H2,H5,H6,J3,J4,J5,J25.J28,K6,K30,L1,L25,L27,M3,M6,(M12),(M13),(M14),(M15),(M16),(M17),(M18),(M19),N1,(N12,(N13),(N14),(N15),(N16),(N17),(N18),(N19),N25,N28,P6,(P12),(P13),(P14),(P15),(P16),(P17),(P18),(P19),P30,R3,(R12),(R13),(R14),(R15),(R16),(R17),(R18),(R19),R25,R27,T1,T6,(T12),(T13),(T14),(T15),(T16),(T17),(T18),(T19),U3,U5,(U12),(U13),(U14),(U15),(U16),(U17),(U18),(U19),U25,U28,V6,(V12),(V13),(V14),(V15),(V16),(V17),(V18),(V19),V30,W1,W5,(W12),(W13),(W14),(W15),(W16),(W17),(W18),(W19),W25,W27,Y3,Y6,AA25,AA28,AB1,AB6,AB30,AC3,AC25,AC27,AD6,AE1,AE5,AE7,AE9,AE11,AE15,AE17,AE21,AE23,AE25,AE26,AE28,AF3,AF5,AF6,AF8,AF10,AF12,AF14,AF15,AF17,AF18,AF19,AF20,AF22,AF24,AF26,AF28,AF30,AG4,AG6,AG8,AG10,AG12,AG14,AG16,AG18,AG23,AG25,AG27,AG29,AH1,AH2,AH3,AH4,AH6,AH8,AH10,AH12,AH14,AH16,AH18,AH21,AH23,AH25,AH27,AH29,AH30,AJ1,AJ3,AJ5,AJ7,AJ9,AJ11,AJ13,AJ15,AJ17,AJ22,AJ24,AJ26,AJ28,AJ30,AK1,AK3,AK5,AK7,AK9,AK11,AK13,AK15,AK17,AK22,AK24,AK26,AK28,AK30RTNGND for all power supplies. Ball numbers in parenthesis are also used as thermal balls and are located within the package center region.
VPGMG25Manufacturing use only (efuse); must be tied to ground
(1) See Table 4-13 for more information on I/O definitions.
Table 4-13 I/O Type Subscript Definition
TYPESUPPLY REFERENCEESD STRUCTURE
SUBSCRIPTDESCRIPTION
11.8V SERDES (VX1)VAD18_VX1ESD diode to supply rail and GND
21.8V LVDS (LS DMD)VAD18_LSIFESD diode to supply rail and GND
31.8V LMCMOS (LS DMD)VAD18_LSIFESD diode to supply rail and GND
43.3V OpenDrain (VX1)VDD33ESD diode to supply rail and GND
53.3V LVDS (FPD)VDD33_FPDESD diode to supply rail and GND
63.3V LVCMOS (PP)VDD33_FPDESD diode to supply rail and GND
71.15V HSSI (HS DMD)VAD115_HSSIESD diode to supply rail and GND
83.3V LVCMOS I/O (8ma output drive - GPIO, etc. )VDD33ESD diode to supply rail and GND
93.3V LVCMOS I/O (OSC)VAD33_OSCAESD diode to GND
103.3V LVCMOS I/O (OSC)VAD33_OSCAESD diode to supply rail and GND
113.3V USB (USB)VAD33_USBESD diode and LBJT to GND
123.3V LVCMOS (USB)VAD33_USBESD diode to supply rail and GND
133.3V OpenDrain (I2C)VDD33ESD diode to supply rail and GND
143.3V LVCMOS I/O (OSC)VAD33_OSCBESD diode to GND
153.3V LVCMOS I/O (OSC)VAD33_OSCBESD diode to supply rail and GND
TYPE
IInputN/A
OOutput
BBidirectional
PWRPower
RTNGround return
Table 4-14 Internal Pullup and Pulldown Characteristics
INTERNAL PULLUP AND PULLDOWN
RESISTOR CHARACTERISTICS(1)		CONDITIONSMINMAXUNIT
Weak pullup resistanceVIN = 0.8V, VDD33 = 3.3V1950kΩ
VIN = 2.0V, VDD33 = 3.3V1239kΩ
(1) An external 5.7kΩ or less pullup or pulldown resistor (if needed) is sufficient for any voltage condition to correctly override any associated internal pullup or pulldown resistance.