DLPS167A March 2024 – September 2024 DLPC964
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Bit(s) | Description | Reset | Type | Notes |
---|---|---|---|---|
0 | Fieldname: HSS_CH0_STATUS_FLD | 0x0 | r | |
1: HSS Channel 0 up | ||||
0: Channel 0 Down | ||||
1 | Fieldname: HSS_CH1_STATUS_FLD | 0x0 | r | |
1: HSS Channel 1 up | ||||
0: Channel 1 Down | ||||
2 | Fieldname: HSS_CH2_STATUS_FLD | 0x0 | r | |
1: HSS Channel 2 up | ||||
0: Channel 2 Down | ||||
3 | Fieldname: HSS_CH1_STATUS_FLD | 0x0 | r | |
1: HSS Channel 3 up | ||||
0: Channel 3 Down | ||||
4 | Fieldname: HSS_USERCLK_NOTLOCK_FLD | 0x0 | r | |
1: user clock not lock | ||||
0: lock | ||||
5 | Fieldname: HSS_GT0PLL_LOCK_FLD | 0x0 | r | |
1: GT0 PLL lock. GT0 PLL is the source for the MMCM to generate user clock | ||||
31:6 | Fieldname: Reserved | 0x0 |