DLPS167A March 2024 – September 2024 DLPC964
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Layer changes should be minimized for single-ended signals.
Individual differential pairs of a bus can be routed on different layers, but the signals of a given pair should not change layers.
Stubs should be avoided.
Low-frequency signals should be routed on the outer layers.
Differential pair signals should be prioritized and routed first.
10-Gbps Aurora 64B/66B differential signals should have vias back-drilled to improve signal integrity.
Pin swapping on components is not allowed.
Polarized capacitors should be drawn with the same orientation.
The PCB should have a solder mask on the top and bottom layers.
The solder mask should not cover the vias.
Except for fine pitch devices (pitch ≤ 0.032 inches), the copper pads and the solder mask cutout should be of the same size.
Solder mask between pads of fine pitch devices should be removed.
In the BGA package, the copper pads and the solder mask cutout should be of the same size.
High-speed connectors that meet the following requirements should be used:
For the 10Gbps Aurora 64B/66B interface:
Differential crosstalk: <1%
Differential impedance: 100Ω ±10%
Insertion loss of the total connector/cabling system should be: <3dB at 5GHz.
For the 3.6Gbps HSSI DMD interface:
Differential crosstalk: <1%
Differential impedance: 100Ω ±10%
Insertion Loss of the total connector/cabling system should be: <3dB at 1.8GHz.