The PWRGOOD signal input to the DLPC964
controller allows the controller to monitor that external power and all pertinent power
supplies for the DLPC964 controller are within proper regulation. When powering up, the
DLPC964 controller is held in reset until the PWRGOOD signal is asserted high. If there
is a loss of external power to the power supplies for the DLPC964 controller or a loss
of power from one of the DLPC964 power supplies, the PWRGOOD signal input to the DLPC964
controller should be asserted low to indicate a loss of power has occurred. Once PWRGOOD
is asserted low, the DLPC964 controller immediately performs a sequence of memory loads
to the DMD followed by the mirror park instruction so that the mirrors end up in an
un-landed state. See
Park Control for more information about parking the
DMD.
The DMDPOWERGOOD signal input to the DLPC964 controller
allows the controller to monitor all pertinent power supplies for the attached DMD. The
interface bus to the attached DMD is not initiated until the DMDPWRGOOD signal is
asserted high, indicating that the power supplies are within regulation. If DMDPWRGOOD
is ever asserted low during operation, the DLPC964 will update the
MAIN_STATUS_DMDPWRGOOD_FLD Register Value in the FPGA_MAIN_STATUS
Register and trigger the IRQZ output to the Applications FPGA or customer
front end.