DLPS167 March 2024 DLPC964
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
It may take longer to complete an MCP on a block than it does to load a block. The single block load time for the DLP991U DMD is outlined in Table 6-8.
DMD | ARRAY | MIRROR SETTLING TIME (μs) | SINGLE ROW LOAD TIME (ns) | SINGLE BLOCK LOAD TIME (μs) | GLOBAL RESET MODE FULL ARRAY (PATTERNS/SECOND) | QUAD BLOCK RESET MODE FULL ARRAY (PATTERNS/SECOND) |
---|---|---|---|---|---|---|
DLP991U | 4096 × 2176 | 4 | 37.09 | 5.04 | 11,273 | 12,390 |
See Section 7.3.1.3 for input data timing description and requirements for any case which involves sending an MCP, block clear, or block set without data loading.
To fully utilize the DMD bandwidth, load four blocks and then concurrently issue an MCP to the four blocks by setting BLKMODE_[1:0] to 10 and BLKADDR_[3:0] to the proper address for the four blocks being reset. This is illustrated in Figure 6-7.
It is possible to load other blocks while the block(s) previously issued an MCP is settling. This is illustrated in Figure 6-6 and Figure 6-7, where blocks are reloaded while the mirror settling time is occurring. It is also possible to load other blocks while previously loaded block(s) have an outstanding MCPn_ACTIVE. This is illustrated in Figure 6-7, where block 0 is loaded while MCPn_ACTIVE is asserted for blocks 12–15.
The DLPC964 controller handles all timing activities related to the Mirror Clocking Pulse, including setup and hold timing to reset of each block, the reset waveform generation timing, and any constraints on loading, clearing, fast clearing, or resetting adjacent or non-adjacent blocks. The DLPC964 controller holds off from accepting loading or clearing commands for a specific block while an MCP is in progress.