DLPS167 March 2024 DLPC964
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The data input interface is based upon the Advanced Micro Devices (AMD) LogiCORETM IP Aurora 64B/66B core, and consists of four input data buses each made up of three high-speed serial data lanes: CH0_GTRX0..2, CH1_GTRX0..2, CH2_GTRX0..2, and CH3_GTRX0..2.
Each bus also includes a Data Clock for each of the four high-speed data lanes: GTTX_CH0_REFCLK, GTTX_CH1_REFCLK, GTTX_CH2_REFCLK, and GTTX_CH3_REFCLK.