DLPS167A March 2024 – September 2024 DLPC964
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
As described in Table 6-5, block clear and block set operations are controlled through the use of the LOAD_TYPE bits in the block control word sent to the DLPC964 through the Aurora 64B/66B interface at the beginning of a DMD action. When the block clear operation is requested, the SRAM cells in the desired block(s) are written with logic zero data. When the block set operation is requested, the SRAM cells in the desired block(s) are written with logic one data. Both of these load types do not require mirror data to be input to the DLPC964 or mirror data to be sent from the DLPC964 to the DMD.