DLPS167 March 2024 DLPC964
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The DLPC964 controller provides an output signal to the Applications FPGA or customer front-end named BLKLOADZ that frames the loading of the most recently received block of data as it is being written to the DMD. This signal shall transition low when a DMD block load begins over the HSSI DMD interface and shall transition back high when the DMD block load is complete.