SPRS976E November 2016 – May 2018 DM505
PRODUCTION DATA.
The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to external SPI devices. This module has a memory mapped register interface, which provides a direct interface for accessing data from external SPI devices and thus simplifying software requirements. It works as a master only. There is one QSPI module in the device and it is primary intended for fast booting from quad-SPI flash memories.
General SPI features:
NOTE
For more information, see the Quad Serial Peripheral Interface section of the Device TRM.
CAUTION
The IO Timings provided in this section are only valid when all QSPI Chip Selects used in a system are configured to use the same Clock Mode (either Clock Mode 0 or Clock Mode 3).
Table 5-49 and Table 5-50 present Timing and Switching Characteristics for Quad SPI Interface.
No | PARAMETER | DESCRIPTION | Mode | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
1 | tc(SCLK) | Cycle time, sclk | Default Timing Mode, Clock Mode 0 | 10.4 | ns | |
Default Timing Mode, Clock Mode 3 | 15.625 | ns | ||||
2 | tw(SCLKL) | Pulse duration, sclk low | Y×P-1 (1) | ns | ||
3 | tw(SCLKH) | Pulse duration, sclk high | Y×P-1 (1) | ns | ||
4 | td(CS-SCLK) | Delay time, sclk falling edge to cs active edge, CS3:0 | Default Timing Mode | -M×P-1 (2)(3) | -M×P+1 (2)(3) | ns |
5 | td(SCLK-CS) | Delay time, sclk falling edge to cs inactive edge, CS3:0 | Default Timing Mode | N×P-1 (2)(3) | N×P+1 (2)(3) | ns |
6 | td(SCLK-D1) | Delay time, sclk falling edge to d[0] transition | Default Timing Mode | -1 | 1 | ns |
7 | tena(CS-D1LZ) | Enable time, cs active edge to d[0] driven (lo-z) | -P-3.5 | -P+2.5 | ns | |
8 | tdis(CS-D1Z) | Disable time, cs active edge to d[0] tri-stated (hi-z) | -P-2.5 | -P+2.0 | ns | |
9 | td(SCLK-D1) | Delay time, sclk first falling edge to first d[0] transition | PHA=0 Only, Default Timing Mode | -1-P | -1-P | ns |
No | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
12 | tsu(D-RTCLK) | Setup time, d[3:0] valid before falling rtclk edge | Default Timing Mode, Clock Mode 0 | 2.9 | ns | |
tsu(D-SCLK) | Setup time, d[3:0] valid before falling sclk edge | Default Timing Mode, Clock Mode 3 | 5.7 | ns | ||
13 | th(RTCLK-D) | Hold time, d[3:0] valid after falling rtclk edge | Default Timing Mode, Clock Mode 0 | -0.1 | ns | |
th(SCLK-D) | Hold time, d[3:0] valid after falling sclk edge | Default Timing Mode, Clock Mode 3 | 0.1 | ns | ||
14 | tsu(D-SCLK) | Setup time, final d[3:0] bit valid before final falling sclk edge | Default Timing Mode, Clock Mode 3 | 5.7-P (1) | ns | |
15 | th(SCLK-D) | Hold time, final d[3:0] bit valid after final falling sclk edge | Default Timing Mode, Clock Mode 3 | 0.1+P (1) | ns |
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-28 and described in Device TRM, Control Module section.
CAUTION
The IO timings provided in this section are only valid if signals within a single IOSET are used. The IOSETs are defined in Table 5-51.
In Table 5-51 are presented the specific groupings of signals (IOSET) for use with QSPI.
SIGNALS | IOSET1 | IOSET2 | IOSET3 | IOSET4 | ||||
---|---|---|---|---|---|---|---|---|
BALL | MUX | BALL | MUX | BALL | MUX | BALL | MUX | |
qspi1_sclk | C8 | 1 | C8 | 1 | C8 | 1 | C8 | 1 |
qspi1_rtclk | C14 | 8 | B7 | 1 | F13 | 5 | D8 | 2 |
qspi1_d0 | B9 | 1 | B9 | 1 | B9 | 1 | B9 | 1 |
qspi1_d1 | F10 | 1 | F10 | 1 | F10 | 1 | F10 | 1 |
qspi1_d2 | A9 | 1 | A9 | 1 | A9 | 1 | A9 | 1 |
qspi1_d3 | D10 | 1 | D10 | 1 | D10 | 1 | D10 | 1 |
qspi1_cs0 | E10 | 1 | E10 | 1 | E10 | 1 | E10 | 1 |
qspi1_cs1 | F15 | 5 | F15 | 5 | F15 | 5 | F15 | 5 |