SNLS647G december 2019 – july 2023 DP83826E , DP83826I
PRODUCTION DATA
There are several loopback options within the DP83826 that test and verify various functional blocks within the PHY. Enabling loopback modes allow for in-circuit testing of the digital and analog data paths. The DP83826 may be configured to any one of the Near-end Loopback modes or to the far-end (reverse) loopback mode. MII loopback is configured using the BASIC mode Control Register (BMCR, address 0x0000). All other loopback modes are enabled using the BIST Control Register (BISCR, address 0x0016). Except where otherwise noted, loopback modes are supported for all speeds (10/100 Mbps and all MAC interfaces).