6 Pin Configuration and Functions (ENHANCED Mode)

The ENHANCED mode is one of two modes that the DP83826 can be configured in at start-up. This mode allows the DP83826 to support real-time Ethernet applications in addition to the standard Ethernet applications. To configure the DP83826 to ENHANCED mode, leave ModeSelect (pin 1) unconnected or pull up with a resistor to VDDIO.

Figure 6-1 RHB Package
32-Pin QFN
(Top View)

Table 6-1 Pin Functions (ENHANCED Mode)

PIN		TYPE ⁽¹⁾	DESCRIPTION
NAME	NO	TYPE ⁽¹⁾	DESCRIPTION
ModeSelect	1	Reset: I, PU Active: I, PU	This pin selects the DP83826 operating mode: BASIC mode or ENHANCED mode. For ENHANCED mode, this pin shall be left NC or pulled-up with a resistor to VDDIO. For BASIC mode, this pin shall be shorted to GND.
CEXT	2	A	External capacitor: Connect the CEXT pin through a 2-nF capacitor to GND.
VDDA3V3	3	Power	Input analog supply: 3V3. For decoupling capacitor requirements, refer to Power Supply Recommendations section of data sheet.
RD_M	4	A	Differential receive input (physical media dependent: PMD): These differential inputs are automatically configured to accept either 10BASE-Te, 100BASE-TX specific signaling mode.
RD_P	5	A
TD_M	6	A	Differential transmit output (PMD): These differential outputs are configured to either 10BASE-Te or 100BASE-TX signaling mode based on configuration chosen for PHY.
TD_P	7	A
XO	8	A	Crystal output: Reference clock output. XO pin is used for crystal only. Leave this pin floating when a CMOS-level oscillator is connected to XI.
XI/50MHzIn	9	A	Crystal or oscillator input clock: MII mode, RMII master mode: 25-MHz ±50 ppm-tolerance crystal or oscillator clock. RMII slave mode: 50-MHz ±50 ppm-tolerance CMOS-level oscillator clock.
RBIAS	10	A	RBIAS ( Bias resistor) value 6.49 kΩ with 1% precision connected to ground.
MDIO	11	Reset: I, PU Active: I/O, PU	Management data I/O: Bi-directional management data signal that may be sourced by the management station or the PHY. This pin has internal pullup resistor of 10 kΩ. An external pullup resistor can be added if needed.
MDC	12	Reset: I, PD Active: I, PD	Management data clock: Synchronous clock to the MDIO serial management input/output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25 MHz. There is no minimum clock rate.
RX_D3	13	Reset: I, PD Active: O Strap7	Receive data: Symbols received on the cable are decoded and presented on these pins synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A nibble RX_D[3:0] is received in MII mode. 2-bits RX_D[1:0] is received in RMII mode.
RX_D2	14	Reset: I, PD Active: O Strap8
RX_D1	15	Reset: I, PD Active: O Strap9
RX_D0	16	Reset: I, PD Active: O Strap0
VDDIO	17	Power	I/O supply voltage: 3.3 V/1.8 V. For decoupling capacitor requirements, refer to Power Supply Decoupling Recommendations section of data sheet.
RX_DV/ CRS_DV	18	Reset: I, PD Active: O Strap10	Receive data valid: This pin indicates valid data is present on the RX_D[3:0] for MII mode and on RX_D[1:0] in RMII mode. In MII mode, this pin acts as RX_DV. In RMII mode, this pin acts as CRS_DV and combines the RMII Carrier and Receive Data Valid indications. This pin can be configured to RX_DV in RMII mode to enable RMII Repeater Mode.
RX_CLK/ 50MHz_RMII	19	Reset: I, PD Active: O	MII receive clock: MII Receive Clock provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed, which is derived from the received data stream. In RMII Master mode, this provides 50-MHz reference clock. In RMII Slave mode, this pin is not used and remains Input, pulldown.
RX_ER	20	Reset: I, PD Active: O Strap6	Receive error: This pin indicates that an error symbol has been detected within a received packet in both MII and RMII mode. In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK. In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference clock. RX_ER is asserted high for every reception error, including errors during Idle. This strap only latches on power-up and not on pin reset.
PWRDN/INT	21	Reset: I, PU Active: I, PU	Power down (default), interrupt: The default function of this pin is power down. Register access is required to configure this pin as an interrupt. In power down function, an active low signal on this pin places the device in power down mode. When this pin is configured as an interrupt pin, this pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with a weak internal pullup resistor (9.5 kΩ). Some applications may require an external PU resistor.
TX_CLK	22	Reset: I, PD Active: O Strap5	MII transmit clock: MII transmit clock provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed. Note that in MII mode, this clock has constant phase referenced to the input clock. Unused in RMII Mode.
TX_EN	23	Reset: I, PD Active: I, PD	Transmit enable: TX_EN is presented on the rising edge of the TX_CLK. TX_EN indicates the presence of valid data inputs on TX_D[3:0] in MII mode and on TX_D[1:0] in RMII mode. TX_EN is an active high signal.
TX_D0	24	Reset: I, PD Active: I, PD	Transmit data: In MII mode, the transmit data nibble received from the MAC is synchronous to the rising edge of TX_CLK. In RMII mode, TX_D[1:0] received from the MAC is synchronous to the rising edge of the reference clock.
TX_D1	25	Reset: I, PD Active: I, PD
TX_D2	26	Reset: I, PD Active: I, PD
TX_D3	27	Reset: I, PD Active: I, PD
COL/LED2/TX_ER GPIO	28	Reset: I, PD Active: O Strap4	Collision Detect (default): In MII mode when the pin is acting as Collision Detect (COL), this pin is always LOW in Full Duplex mode. In Half Duplex mode, COL is asserted HIGH only when both transmit and receive media are non-idle. This pin can also be configured as a second additional LED driver (LED2), the MII TX_ER signal or general purpose I/O (GPIO) through register configurations. In RMII mode, this pin acts as LED2 by default.
CRS/LED3	29	Reset: I, PD Active: O Strap3	Carrier sense (default): In MII mode this pin is asserted high when the receive or transmit medium is non-idle. Carrier sense and receive data valid. This pin can be configured as third LED (LED3) through register configuration. In RMII mode, it is configured as LED3 by default.
LED0	30	Reset: I, PD Active: O Strap2	LED0: This LED indicates transmit and receive activity in addition to the status of the Link. The LED is ON when link is good. The LED blinks when the transmitter or receiver is active. LED polarity is auto-detected (Active Low/ Active High) based on external pull-up or pull-down on the pin.
CLKOUT/ LED1	31	Reset: I, PU Active: O Strap1	This pin provides 25-MHz reference clock from XI as default output after power-on reset (POR). The output is not affected by Resets allowing Application to reset PHY without impacting other system getting impacted. The output clock switches off only by Deep Power Down. The pin can be configured to act as LED1 using strap or register configuration. The strap only latches on power-up and not on pin reset. The LED is ON when link is 100 M. LED remains OFF if Link is 10 M or no Link. LED polarity is auto-detected (Active Low/ Active High) based on external pull-up or pull-down on the pin. This strap only latches on power-up and not on pin reset.
RST_N	32	Reset: I, PU Active: I, PU	Reset low: RST_N pin is an active low reset input. Asserting this pin low for at least 25 μs forces a reset process to occur. Initiation of reset causes strap pins to be re-scanned and resets all the internal registers of the PHY to default value.

(1) I = Input, O = Output, I/O = Input/Ouput, A = Analog, PU or PD = Internal pullup or pulldown: Hardware bootstrap configuration