SNLS604E September   2020  – November 2022 DP83TG720S-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2. 5.1 Pin States
    3. 5.2 Pin Power Domain
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 LED Drive Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Diagnostic Tool Kit
        1. 7.3.1.1 Signal Quality Indicator
        2. 7.3.1.2 Time Domain Reflectometry
        3. 7.3.1.3 Built-In Self-Test For Datapath
          1. 7.3.1.3.1 Loopback Modes
          2. 7.3.1.3.2 Data Generator
          3. 7.3.1.3.3 Programming Datapath BIST
        4. 7.3.1.4 Temperature and Voltage Sensing
        5. 7.3.1.5 Electrostatic Discharge Sensing
      2. 7.3.2 Compliance Test Modes
        1. 7.3.2.1 Test Mode 1
        2. 7.3.2.2 Test Mode 2
        3. 7.3.2.3 Test Mode 4
        4. 7.3.2.4 Test Mode 5
        5. 7.3.2.5 Test Mode 6
        6. 7.3.2.6 Test Mode 7
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Down
      2. 7.4.2  Reset
      3. 7.4.3  Standby
      4. 7.4.4  Normal
      5. 7.4.5  Sleep
      6. 7.4.6  State Transitions
        1. 7.4.6.1 State Transition #1 - Standby to Normal
        2. 7.4.6.2 State Transition #2 - Normal to Standby
        3. 7.4.6.3 State Transition #3 - Normal to Sleep
        4. 7.4.6.4 State Transition #4 - Sleep to Normal
      7. 7.4.7  Media Dependent Interface
        1. 7.4.7.1 MDI Master and MDI Slave Configuration
        2. 7.4.7.2 Auto-Polarity Detection and Correction
      8. 7.4.8  MAC Interfaces
        1. 7.4.8.1 Reduced Gigabit Media Independent Interface
        2. 7.4.8.2 Serial Gigabit Media Independent Interface
      9. 7.4.9  Serial Management Interface
      10. 7.4.10 Direct Register Access
      11. 7.4.11 Extended Register Space Access
      12. 7.4.12 Write Address Operation
        1. 7.4.12.1 Example - Write Address Operation
      13. 7.4.13 Read Address Operation
        1. 7.4.13.1 Example - Read Address Operation
      14. 7.4.14 Write Operation (No Post Increment)
        1. 7.4.14.1 Example - Write Operation (No Post Increment)
      15. 7.4.15 Read Operation (No Post Increment)
        1. 7.4.15.1 Example - Read Operation (No Post Increment)
      16. 7.4.16 Write Operation (Post Increment)
        1. 7.4.16.1 Example - Write Operation (Post Increment)
      17. 7.4.17 Read Operation (Post Increment)
        1. 7.4.17.1 Example - Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 PHY Address Configuration
    6. 7.6 Register Maps
      1. 7.6.1 Register Access Summary
      2. 7.6.2 DP83TG720 Registers
        1. 7.6.2.1 Base Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
  9. 9 Power Supply Recommendations
  10. 10Compatibility with TI's 100BT1 PHY
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Physical Medium Attachment
      4. 11.1.4 Metal Pour
      5. 11.1.5 PCB Layer Stacking
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.2 DP83TG720 Registers

Table 7-23 lists the memory-mapped registers for the DP83TG720 registers. All register offset addresses not listed in Table 7-23 should be considered as reserved locations and the register contents should not be modified.

Table 7-23 DP83TG720 Registers
OffsetAcronymRegister NameSection
0hBMCR#DP83TG720_DP83TG720_DP83TG720_MII_REG_0
1hBMSR#DP83TG720_DP83TG720_DP83TG720_MII_REG_1
2hPHYID1#DP83TG720_DP83TG720_DP83TG720_MII_REG_2
3hPHYID2#DP83TG720_DP83TG720_DP83TG720_MII_REG_3
DhREGCR#DP83TG720_DP83TG720_DP83TG720_REGCR
EhADDAR#DP83TG720_DP83TG720_DP83TG720_ADDAR
10hMII_REG_10#DP83TG720_DP83TG720_DP83TG720_MII_REG_10
11hMII_REG_11#DP83TG720_DP83TG720_DP83TG720_MII_REG_11
12hMII_REG_12#DP83TG720_DP83TG720_DP83TG720_MII_REG_12
13hMII_REG_13#DP83TG720_DP83TG720_DP83TG720_MII_REG_13
16hMII_REG_16#DP83TG720_DP83TG720_DP83TG720_MII_REG_16
18hMII_REG_18#DP83TG720_DP83TG720_DP83TG720_MII_REG_18
19hMII_REG_19#DP83TG720_DP83TG720_DP83TG720_MII_REG_19
1EhMII_REG_1E#DP83TG720_DP83TG720_DP83TG720_MII_REG_1E
1FhMII_REG_1F#DP83TG720_DP83TG720_DP83TG720_MII_REG_1F
180hLSR#DP83TG720_DP83TG720_DP83TG720_LSR
18BhLPS_CFG2#DP83TG720_DP83TG720_DP83TG720_LPS_CFG2
18ChLPS_CFG3#DP83TG720_DP83TG720_DP83TG720_LPS_CFG3
309hTDR_STATUS0#DP83TG720_DP83TG720_DP83TG720_TDR_STATUS0
30AhTDR_STATUS1#DP83TG720_DP83TG720_DP83TG720_TDR_STATUS1
30BhTDR_STATUS2#DP83TG720_DP83TG720_DP83TG720_TDR_STATUS2
30EhTDR_STATUS5#DP83TG720_DP83TG720_DP83TG720_TDR_STATUS5
30FhTDR_TC12#DP83TG720_DP83TG720_DP83TG720_TDR_TC12
405hA2D_REG_05#DP83TG720_DP83TG720_DP83TG720_A2D_REG_05
41EhA2D_REG_30#DP83TG720_DP83TG720_DP83TG720_A2D_REG_30
41FhA2D_REG_31#DP83TG720_DP83TG720_DP83TG720_A2D_REG_31
428hA2D_REG_40#DP83TG720_DP83TG720_DP83TG720_A2D_REG_40
429hA2D_REG_41#DP83TG720_DP83TG720_DP83TG720_A2D_REG_41
42BhA2D_REG_43#DP83TG720_DP83TG720_DP83TG720_A2D_REG_43
42ChA2D_REG_44#DP83TG720_DP83TG720_DP83TG720_A2D_REG_44
42EhA2D_REG_46#DP83TG720_DP83TG720_DP83TG720_A2D_REG_46
42FhA2D_REG_47#DP83TG720_DP83TG720_DP83TG720_A2D_REG_47
430hA2D_REG_48#DP83TG720_DP83TG720_DP83TG720_A2D_REG_48
442hA2D_REG_66#DP83TG720_DP83TG720_DP83TG720_A2D_REG_66
450hLEDS_CFG_1#DP83TG720_DP83TG720_DP83TG720_LEDS_CFG_1
451hLEDS_CFG_2#DP83TG720_DP83TG720_DP83TG720_LEDS_CFG_2
452hIO_MUX_CFG_1#DP83TG720_DP83TG720_DP83TG720_IO_MUX_CFG_1
453hIO_MUX_CFG_2#DP83TG720_DP83TG720_DP83TG720_IO_MUX_CFG_2
454hIO_CONTROL_1#DP83TG720_DP83TG720_DP83TG720_IO_CONTROL_1
455hIO_CONTROL_2#DP83TG720_DP83TG720_DP83TG720_IO_CONTROL_2
456hIO_CONTROL_3#DP83TG720_DP83TG720_DP83TG720_IO_CONTROL_3
457hIO_STATUS_1#DP83TG720_DP83TG720_DP83TG720_IO_STATUS_1
458hIO_STATUS_2#DP83TG720_DP83TG720_DP83TG720_IO_STATUS_2
459hIO_CONTROL_4#DP83TG720_DP83TG720_DP83TG720_IO_CONTROL_4
45AhIO_CONTROL_5#DP83TG720_DP83TG720_DP83TG720_IO_CONTROL_5
45DhSOR_VECTOR_1#DP83TG720_DP83TG720_DP83TG720_SOR_VECTOR_1
45EhSOR_VECTOR_2#DP83TG720_DP83TG720_DP83TG720_SOR_VECTOR_2
467hMONITOR_CTRL1#DP83TG720_DP83TG720_DP83TG720_MONITOR_CTRL1
468hMONITOR_CTRL2#DP83TG720_DP83TG720_DP83TG720_MONITOR_CTRL2
46AhMONITOR_CTRL4#DP83TG720_DP83TG720_DP83TG720_MONITOR_CTRL4
47BhMONITOR_STAT1#DP83TG720_DP83TG720_DP83TG720_MONITOR_STAT1
50AhBREAK_LINK_TIMER#DP83TG720_DP83TG720_DP83TG720_BREAK_LINK_TIMER
510hRS_DECODER#DP83TG720_DP83TG720_DP83TG720_RS_DECODER
514hLPS_CONTROL_1#DP83TG720_DP83TG720_DP83TG720_LPS_CONTROL_1
515hLPS_CONTROL_2#DP83TG720_DP83TG720_DP83TG720_LPS_CONTROL_2
518hMAXWAIT_TIMER#DP83TG720_DP83TG720_DP83TG720_MAXWAIT_TIMER
519hPHY_CTRL_1G#DP83TG720_DP83TG720_DP83TG720_PHY_CTRL_1G
531hTEST_MODE#DP83TG720_DP83TG720_DP83TG720_TEST_MODE
543hLINK_QUAL_1#DP83TG720_DP83TG720_DP83TG720_LINK_QUAL_1
544hLINK_QUAL_2#DP83TG720_DP83TG720_DP83TG720_LINK_QUAL_2
545hLINK_DOWN_LATCH_STAT#DP83TG720_DP83TG720_DP83TG720_LINK_DOWN_LATCH_STAT
547hLINK_QUAL_3#DP83TG720_DP83TG720_DP83TG720_LINK_QUAL_3
548hLINK_QUAL_4#DP83TG720_DP83TG720_DP83TG720_LINK_QUAL_4
552hRS_DECODER_FRAME_STAT_2#DP83TG720_DP83TG720_DP83TG720_RS_DECODER_FRAME_STAT_2
559hPMA_WATCHDOG#DP83TG720_DP83TG720_DP83TG720_PMA_WATCHDOG
55BhSYMB_POL_CFG#DP83TG720_DP83TG720_DP83TG720_SYMB_POL_CFG
55ChOAM_CFG#DP83TG720_DP83TG720_DP83TG720_OAM_CFG
561hTEST_MEM_CFG#DP83TG720_DP83TG720_DP83TG720_TEST_MEM_CFG
573hFORCE_CTRL1#DP83TG720_DP83TG720_DP83TG720_FORCE_CTRL1
600hRGMII_CTRL#DP83TG720_DP83TG720_DP83TG720_RGMII_CTRL
601hRGMII_FIFO_STATUS#DP83TG720_DP83TG720_DP83TG720_RGMII_FIFO_STATUS
602hRGMII_DELAY_CTRL#DP83TG720_DP83TG720_DP83TG720_RGMII_DELAY_CTRL
608hSGMII_CTRL_1#DP83TG720_DP83TG720_DP83TG720_SGMII_CTRL_1
60AhSGMII_STATUS#DP83TG720_DP83TG720_DP83TG720_SGMII_STATUS
60ChSGMII_CTRL_2#DP83TG720_DP83TG720_DP83TG720_SGMII_CTRL_2
60DhSGMII_FIFO_STATUS#DP83TG720_DP83TG720_DP83TG720_SGMII_FIFO_STATUS
618hPRBS_STATUS_1#DP83TG720_DP83TG720_DP83TG720_PRBS_STATUS_1
619hPRBS_CTRL_1#DP83TG720_DP83TG720_DP83TG720_PRBS_CTRL_1
61AhPRBS_CTRL_2#DP83TG720_DP83TG720_DP83TG720_PRBS_CTRL_2
61BhPRBS_CTRL_3#DP83TG720_DP83TG720_DP83TG720_PRBS_CTRL_3
61ChPRBS_STATUS_2#DP83TG720_DP83TG720_DP83TG720_PRBS_STATUS_2
61DhPRBS_STATUS_3#DP83TG720_DP83TG720_DP83TG720_PRBS_STATUS_3
61EhPRBS_STATUS_4#DP83TG720_DP83TG720_DP83TG720_PRBS_STATUS_4
620hPRBS_STATUS_6#DP83TG720_DP83TG720_DP83TG720_PRBS_STATUS_6
622hPRBS_STATUS_8#DP83TG720_DP83TG720_DP83TG720_PRBS_STATUS_8
623hPRBS_STATUS_9#DP83TG720_DP83TG720_DP83TG720_PRBS_STATUS_9
624hPRBS_CTRL_4#DP83TG720_DP83TG720_DP83TG720_PRBS_CTRL_4
625hPRBS_CTRL_5#DP83TG720_DP83TG720_DP83TG720_PRBS_CTRL_5
626hPRBS_CTRL_6#DP83TG720_DP83TG720_DP83TG720_PRBS_CTRL_6
627hPRBS_CTRL_7#DP83TG720_DP83TG720_DP83TG720_PRBS_CTRL_7
628hPRBS_CTRL_8#DP83TG720_DP83TG720_DP83TG720_PRBS_CTRL_8
629hPRBS_CTRL_9#DP83TG720_DP83TG720_DP83TG720_PRBS_CTRL_9
62AhPRBS_CTRL_10#DP83TG720_DP83TG720_DP83TG720_PRBS_CTRL_10
638hCRC_STATUS#DP83TG720_DP83TG720_DP83TG720_CRC_STATUS
639hPKT_STAT_1#DP83TG720_DP83TG720_DP83TG720_PKT_STAT_1
63AhPKT_STAT_2#DP83TG720_DP83TG720_DP83TG720_PKT_STAT_2
63BhPKT_STAT_3#DP83TG720_DP83TG720_DP83TG720_PKT_STAT_3
63ChPKT_STAT_4#DP83TG720_DP83TG720_DP83TG720_PKT_STAT_4
63DhPKT_STAT_5#DP83TG720_DP83TG720_DP83TG720_PKT_STAT_5
63EhPKT_STAT_6#DP83TG720_DP83TG720_DP83TG720_PKT_STAT_6
871hSQI_REG_1#DP83TG720_DP83TG720_DP83TG720_SQI_REG_1
875hDSP_REG_75#DP83TG720_DP83TG720_DP83TG720_DSP_REG_75
8ADhSQI_1#DP83TG720_DP83TG720_DP83TG720_SQI_1
1000hPMA_PMD_CONTROL_1First nibble (0x1) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_PMA_PMD_CONTROL_1
1007hPMA_PMD_CONTROL_2First nibble (0x1) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_PMA_PMD_CONTROL_2
1009hPMA_PMD_TRANSMIT_DISABLEFirst nibble (0x1) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_PMA_PMD_TRANSMIT_DISABLE
100BhPMA_PMD_EXTENDED_ABILITY2First nibble (0x1) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_PMA_PMD_EXTENDED_ABILITY2
1012hPMA_PMD_EXTENDED_ABILITYFirst nibble (0x1) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_PMA_PMD_EXTENDED_ABILITY
1834hPMA_PMD_CONTROLFirst nibble (0x1) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_PMA_PMD_CONTROL
1900hPMA_CONTROLFirst nibble (0x1) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_PMA_CONTROL
1901hPMA_STATUSFirst nibble (0x1) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_PMA_STATUS
1902hTRAININGFirst nibble (0x1) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_TRAINING
1903hLP_TRAININGFirst nibble (0x1) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_LP_TRAINING
1904hTEST_MODE_CONTROLFirst nibble (0x1) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_TEST_MODE_CONTROL
3000hPCS_CONTROL_COPYFirst nibble (0x3) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_PCS_CONTROL_COPY
3900hPCS_CONTROLFirst nibble (0x3) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_PCS_CONTROL
3901hPCS_STATUSFirst nibble (0x3) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_PCS_STATUS
3902hPCS_STATUS_2First nibble (0x3) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_PCS_STATUS_2
3904hOAM_TRANSMITFirst nibble (0x3) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_OAM_TRANSMIT
3905hOAM_TX_MESSAGE_1First nibble (0x3) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_OAM_TX_MESSAGE_1
3906hOAM_TX_MESSAGE_2First nibble (0x3) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_OAM_TX_MESSAGE_2
3907hOAM_TX_MESSAGE_3First nibble (0x3) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_OAM_TX_MESSAGE_3
3908hOAM_TX_MESSAGE_4First nibble (0x3) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_OAM_TX_MESSAGE_4
3909hOAM_RECEIVEFirst nibble (0x3) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_OAM_RECEIVE
390AhOAM_RX_MESSAGE_1First nibble (0x3) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_OAM_RX_MESSAGE_1
390BhOAM_RX_MESSAGE_2First nibble (0x3) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_OAM_RX_MESSAGE_2
390ChOAM_RX_MESSAGE_3First nibble (0x3) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_OAM_RX_MESSAGE_3
390DhOAM_RX_MESSAGE_4First nibble (0x3) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_OAM_RX_MESSAGE_4
7200hAN_CFGFirst nibble (0x7) in the register address is to indicated MMD register space.
For register access, ignore the first nibble.		#DP83TG720_DP83TG720_DP83TG720_AN_CFG

7.6.2.1 BMCR Register (Offset = 0h) [Reset = 0140h]

BMCR is shown in Figure 7-20 and described in Table 7-24.

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Figure 7-20 BMCR Register
15141312111098
mii_resetloopbackRESERVEDRESERVEDpower_downisolateRESERVEDRESERVED
R/WMC-0hR/W-0hR-0hR-0hR/W-0hR/W-0hR-0hR-1h
76543210
RESERVEDspeed_sel_msbRESERVEDRESERVED
R-0hR-1hR-0hR-0h
Table 7-24 BMCR Register Field Descriptions
BitFieldTypeResetDescription
15mii_resetR/WMC0h 1b = Digital in reset and all MII regs (0x0 - 0xF) reset to default 0b = No reset
14loopbackR/W0h 1b = MII loopback 0b = No MII loopback
13RESERVEDR0h Reserved
12RESERVEDR0h Reserved
11power_downR/W0h 1b = Power down via register or pin 0b = Normal mode
10isolateR/W0h 1b = MAC isolate mode (No output to MAC from the PHY) 0b = Normal Mode
9RESERVEDR0h Reserved
8RESERVEDR1h Reserved
7RESERVEDR0h Reserved
6speed_sel_msbR1h 0b= Reserved 1b= 1000 Mb/s
5RESERVEDR0h Reserved
4-0RESERVEDR0h Reserved

7.6.2.2 BMSR Register (Offset = 1h) [Reset = 0141h]

BMSR is shown in Figure 7-21 and described in Table 7-25.

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Figure 7-21 BMSR Register
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDextended_status
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-1h
76543210
unidirectional_abilitypreamble_supressionaneg_completeremote_faultaneg_abilitylink_statusjabber_detectextended_capability
R-0hR-1hR-0hR/W0C-0hR-0hR/W0S-0hR/W0C-0hR-1h
Table 7-25 BMSR Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14RESERVEDR0h Reserved
13RESERVEDR0h Reserved
12RESERVEDR0h Reserved
11RESERVEDR0h Reserved
10RESERVEDR0h Reserved
9RESERVEDR0h Reserved
8extended_statusR1h 1b = Extended status information in Register 15 0b = No extended status information in Register 15
7unidirectional_abilityR0h Reserved
6preamble_supressionR1h 1b = PHY will accept management frames with preamble suppressed. 0b = PHY will not accept management frames with preamble suppressed
5aneg_completeR0h Reserved
4remote_faultR/W0C0h Reserved
3aneg_abilityR0h Reserved
1jabber_detectR/W0C0h Reserved
0extended_capabilityR1h 1b = extended register capabilities 0b = basic register set capabilities only

7.6.2.3 PHYID1 Register (Offset = 2h) [Reset = 2000h]

PHYID1 is shown in Figure 7-22 and described in Table 7-26.

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Figure 7-22 PHYID1 Register
15141312111098
oui_21_16
R-2000h
76543210
oui_21_16
R-2000h
Table 7-26 PHYID1 Register Field Descriptions
BitFieldTypeResetDescription
15-0oui_21_16R2000h Unique identifier for the part

7.6.2.4 PHYID2 Register (Offset = 3h) [Reset = A284h]

PHYID2 is shown in Figure 7-23 and described in Table 7-27.

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Figure 7-23 PHYID2 Register
15141312111098
oui_5_0model_number
R-28hR-28h
76543210
model_numberrev_number
R-28hR-4h
Table 7-27 PHYID2 Register Field Descriptions
BitFieldTypeResetDescription
15-10oui_5_0R28h Unique identifier for the part
9-4model_numberR28h Unique identifier for the part
3-0rev_numberR4h Unique identifier for the part

7.6.2.5 REGCR Register (Offset = Dh) [Reset = 0000h]

REGCR is shown in Figure 7-24 and described in Table 7-28.

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Figure 7-24 REGCR Register
15141312111098
Extended Register CommandRESERVED
R/W-0hR/W-0h
76543210
RESERVEDDEVAD
R/W-0hR/W-0h
Table 7-28 REGCR Register Field Descriptions
BitFieldTypeResetDescription
15-14Extended Register CommandR/W0h 00b = Address 01b = Data, no post increment 10b = Data, post increment on read and write 11b = Data, post increment on write only
13-5RESERVEDR/W0h Reserved
4-0DEVADR/W0h RESERVED

7.6.2.6 ADDAR Register (Offset = Eh) [Reset = 0000h]

ADDAR is shown in Figure 7-25 and described in Table 7-29.

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Figure 7-25 ADDAR Register
15141312111098
Address/Data
R/W-0h
76543210
Address/Data
R/W-0h
Table 7-29 ADDAR Register Field Descriptions
BitFieldTypeResetDescription
15-0Address/DataR/W0h

7.6.2.7 MII_REG_10 Register (Offset = 10h) [Reset = 0004h]

MII_REG_10 is shown in Figure 7-26 and described in Table 7-30.

Return to the Summary Table.

Figure 7-26 MII_REG_10 Register
15141312111098
RESERVEDsignal_detectdescr_lock_bitRESERVED
R-0hR/W0S-0hR/W0S-0hR-0h
76543210
mii_int_bitRESERVEDmii_loopbackduplex_mode_envRESERVEDlink_status_bit
0hR-0hR-0hR-1hR-0hR-0h
Table 7-30 MII_REG_10 Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10signal_detectR/W0S0h 1b = Channel ok is set 0b = Channel ok had been reset
9descr_lock_bitR/W0S0h 1b = Descrambler is locked 0b = Descrmabler had been locked
8RESERVEDR0h Reserved
7mii_int_bit0h 1b = Interrupt pin had been set 0b = Interrupts pin not set
6-4RESERVEDR0h Reserved
3mii_loopbackR0h 1b = MII loopback 0b = No MII loopback
2duplex_mode_envR1h 1b = Full duplex 0b = Half duplex
1RESERVEDR0h Reserved

7.6.2.8 MII_REG_11 Register (Offset = 11h) [Reset = 000Bh]

MII_REG_11 is shown in Figure 7-27 and described in Table 7-31.

Return to the Summary Table.

Figure 7-27 MII_REG_11 Register
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/WSC-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDint_polarityforce_interruptint_enRESERVED
R-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-1h
Table 7-31 MII_REG_11 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13-12RESERVEDR/W0h Reserved
11RESERVEDR/WSC0h Reserved
10RESERVEDR/W0h Reserved
9RESERVEDR/W0h Reserved
8RESERVEDR/W0h Reserved
7RESERVEDR0h Reserved
6RESERVEDR/W0h Reserved
5-4RESERVEDR/W0h Reserved
3int_polarityR/W1h 1b = Active low 0b = Active high
2force_interruptR/W0h 1b = Force interrupt pin 0b = Do not force interrupt pin
1int_enR/W1h 1b = Enable interrupts 0b = Disable interrupts
0RESERVEDR/W1h Reserved

7.6.2.9 MII_REG_12 Register (Offset = 12h) [Reset = 0000h]

MII_REG_12 is shown in Figure 7-28 and described in Table 7-32.

Return to the Summary Table.

Figure 7-28 MII_REG_12 Register
15141312111098
link_qual_intenergy_det_intlink_intRESERVEDesd_intms_train_done_intRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
link_qual_int_enenergy_det_int_enlink_int_enunused_int_3esd_int_enms_train_done_int_enunused_int_2unused_int_1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-32 MII_REG_12 Register Field Descriptions
BitFieldTypeResetDescription
14energy_det_intR0h Energy det change interrupt status
12RESERVEDR0h Reserved
11esd_intR0h ESD fault detected interrupt status
10ms_train_done_intR0h Training done interrupt status
9RESERVEDR0h Reserved
8RESERVEDR0h Reserved
6energy_det_int_enR/W0h Energy det change interrupt enable
4unused_int_3R/W0h Reserved
3esd_int_enR/W0h ESD fault detected interrupt enable
2ms_train_done_int_enR/W0h Training done interrupt enable
1unused_int_2R/W0h Reserved
0unused_int_1R/W0h Reserved

7.6.2.10 MII_REG_13 Register (Offset = 13h) [Reset = 0000h]

MII_REG_13 is shown in Figure 7-29 and described in Table 7-33.

Return to the Summary Table.

Figure 7-29 MII_REG_13 Register
15141312111098
under_volt_intover_volt_intRESERVEDRESERVEDover_temp_intsleep_intpol_change_intnot_one_hot_int
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
under_volt_int_enover_volt_int_enunused_int_6unused_int_5over_temp_int_ensleep_int_enpol_change_int_ennot_one_hot_int_en
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-33 MII_REG_13 Register Field Descriptions
BitFieldTypeResetDescription
15under_volt_intR0h Under volt interrupt status
14over_volt_intR0h Over volt interrupt status
13RESERVEDR0h Reserved
12RESERVEDR0h Reserved
11over_temp_intR0h Over temp interrupt status
10sleep_intR0h Sleep mode change interrupt status
9pol_change_intR0h Data polarity change interrupt status
8not_one_hot_intR0h Not one hot interrupt status
7under_volt_int_enR/W0h Under volt interrupt enable
6over_volt_int_enR/W0h Over volt interrupt enable
5unused_int_6R/W0h Reserved
4unused_int_5R/W0h Reserved
3over_temp_int_enR/W0h Over temp interrupt enable
2sleep_int_enR/W0h Sleep mode change interrupt enable
1pol_change_int_enR/W0h Data Polarity change interrupt enable
0not_one_hot_int_enR/W0h Not one hot interrupt enable

7.6.2.11 MII_REG_16 Register (Offset = 16h) [Reset = 0000h]

MII_REG_16 is shown in Figure 7-30 and described in Table 7-34.

Return to the Summary Table.

Figure 7-30 MII_REG_16 Register
15141312111098
RESERVEDprbs_sync_lossRESERVEDcore_pwr_mode
R-0hR/W0C-0hR-0hR-0h
76543210
cfg_dig_pcs_loopbackloopback_mode
R/W-0hR/W-0h
Table 7-34 MII_REG_16 Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10prbs_sync_lossR/W0C0h 1b = Prbs lock had been lost 0b = Prbs lock never lost
9RESERVEDR0h Reserved
8core_pwr_modeR0h 1b = Core is is normal power mode 0b = Core is in power down or sleep mode
7cfg_dig_pcs_loopbackR/W0h PCS digital loopback
6-0loopback_modeR/W0h 000001b = PCS loop 000010b = RS loop 000100b = Digital loop 001000B = Analog loop 010000b = Reverse loop

7.6.2.12 MII_REG_18 Register (Offset = 18h) [Reset = 0008h]

MII_REG_18 is shown in Figure 7-31 and described in Table 7-35.

Return to the Summary Table.

Figure 7-31 MII_REG_18 Register
15141312111098
ack_received_inttx_valid_clr_intRESERVEDRESERVEDpor_done_intno_frame_intwake_req_intlps_int
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
ack_received_int_entx_valid_clr_int_enRESERVEDRESERVEDpor_done_int_enno_frame_int_enwake_req_int_enlps_int_en
R/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
Table 7-35 MII_REG_18 Register Field Descriptions
BitFieldTypeResetDescription
15ack_received_intR0h Ack received interrupt status (OAM)
14tx_valid_clr_intR0h mr_tx_valid clear interrupt status (OAM)
13RESERVEDR0h Reserved
12RESERVEDR0h Reserved
11por_done_intR0h POR done interrupt status
10no_frame_intR0h No frame detect interrupt status
9wake_req_intR0h Wake request interrupt status
8lps_intR0h LPS interrupt status
7ack_received_int_enR/W0h Ack received interrupt enable (OAM)
6tx_valid_clr_int_enR/W0h mr_tx_valid clear interrupt enable (OAM)
5RESERVEDR/W0h Reserved
4RESERVEDR/W0h Reserved
3por_done_int_enR/W1h POR done interrupt enable
2no_frame_int_enR/W0h No frame detect interrupt enable
1wake_req_int_enR/W0h Wake request interrupt enable
0lps_int_enR/W0h LPS interrupt enable

7.6.2.13 MII_REG_19 Register (Offset = 19h) [Reset = X]

MII_REG_19 is shown in Figure 7-32 and described in Table 7-36.

Return to the Summary Table.

Figure 7-32 MII_REG_19 Register
15141312111098
RESERVEDRESERVEDRESERVED
R-0hR-0hR-0h
76543210
RESERVEDSOR_PHYADDR
R-0hR-X
Table 7-36 MII_REG_19 Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10RESERVEDR0h Reserved
9-5RESERVEDR0h Reserved
4-0SOR_PHYADDRRX PHY ADDRESS latched from strap

7.6.2.14 MII_REG_1E Register (Offset = 1Eh) [Reset = 0000h]

MII_REG_1E is shown in Figure 7-33 and described in Table 7-37.

Return to the Summary Table.

Figure 7-33 MII_REG_1E Register
15141312111098
tdr_startcfg_tdr_auto_runRESERVED
R/WMC-0hR/W-0hR-0h
76543210
RESERVEDtdr_donetdr_fail
R-0hR-0hR-0h
Table 7-37 MII_REG_1E Register Field Descriptions
BitFieldTypeResetDescription
15tdr_startR/WMC0h 1b = TDR start 0b = No TDR
14cfg_tdr_auto_runR/W0h 1b = TDR start automatically on link down 0b = TDR start manually
13-2RESERVEDR0h Reserved
1tdr_doneR0h TDR done status
0tdr_failR0h TDR fail status

7.6.2.15 MII_REG_1F Register (Offset = 1Fh) [Reset = 0000h]

MII_REG_1F is shown in Figure 7-34 and described in Table 7-38.

Return to the Summary Table.

Figure 7-34 MII_REG_1F Register
15141312111098
sw_global_resetdigital_resetRESERVEDRESERVED
R/WMC-0hR/WMC-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR-0hR/W-0h
Table 7-38 MII_REG_1F Register Field Descriptions
BitFieldTypeResetDescription
15sw_global_resetR/WMC0h Hardware reset - Reset digital + register file
14digital_resetR/WMC0h Soft reset - Reset only digital core
13RESERVEDR/W0h Reserved
12-8RESERVEDR/W0h Reserved
7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5RESERVEDR0h Reserved
4-0RESERVEDR/W0h Reserved

7.6.2.16 LSR Register (Offset = 180h) [Reset = 0000h]

LSR is shown in Figure 7-35 and described in Table 7-39.

Return to the Summary Table.

Figure 7-35 LSR Register
15141312111098
link_uplink_downphy_ctrl_send_datalink_statusRESERVED
R-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDdescr_syncloc_rcvr_statusrem_rcvr_status
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 7-39 LSR Register Field Descriptions
BitFieldTypeResetDescription
13phy_ctrl_send_dataR0h Phy control in send data status
11-8RESERVEDR0h Reserved
7RESERVEDR0h Reserved
6RESERVEDR0h Reserved
5RESERVEDR0h Reserved
4RESERVEDR0h Reserved
3RESERVEDR0h Reserved
2descr_syncR0h Descrambler lock status
1loc_rcvr_statusR0h Local receiver status
0rem_rcvr_statusR0h Remote receiver status

7.6.2.17 LPS_CFG2 Register (Offset = 18Bh) [Reset = 0000h]

LPS_CFG2 is shown in Figure 7-36 and described in Table 7-40.

Return to the Summary Table.

Figure 7-36 LPS_CFG2 Register
15141312111098
RESERVEDed_en
R-0hR/W-0h
76543210
sleep_encfg_auto_mode_en_strapcfg_lps_mon_en_strapcfg_lps_sleep_autocfg_lps_slp_confirmcfg_lps_auto_pwrdncfg_lps_sleep_encfg_lps_sm_en
R/W-0hR/WMC,1-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-40 LPS_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0h Reserved
8ed_enR/W0h 1b = Enable energy detection on MDI 0b = Disable energy detection on MDI
7sleep_enR/W0h 1b = Allow PHY to enter sleep 0b = Do not allow PHY to enter sleep
6cfg_auto_mode_en_strapR/WMC,10h LPS autonomous mode enable 1b = PHY enters normal mode on power up 0b = PHY enters standby mode on power up
5cfg_lps_mon_en_strapR/W0h
4cfg_lps_sleep_autoR/W0h Reserved
3cfg_lps_slp_confirmR/W0h Reserved
2cfg_lps_auto_pwrdnR/W0h Reserved
1cfg_lps_sleep_enR/W0h Reserved
0cfg_lps_sm_enR/W0h Reserved

7.6.2.18 LPS_CFG3 Register (Offset = 18Ch) [Reset = 0000h]

LPS_CFG3 is shown in Figure 7-37 and described in Table 7-41.

Return to the Summary Table.

Figure 7-37 LPS_CFG3 Register
15141312111098
RESERVED
R-0h
76543210
cfg_lps_pwr_mode_7cfg_lps_pwr_mode_6cfg_lps_pwr_mode_5cfg_lps_pwr_mode_4cfg_lps_pwr_mode_3cfg_lps_pwr_mode_2cfg_lps_pwr_mode_1cfg_lps_pwr_mode_0
R/WMC,0-0hR/WMC,0-0hR/WMC,0-0hR/WMC,0-0hR/WMC,0-0hR/WMC,0-0hR/WMC,0-0hR/WMC,0-0h
Table 7-41 LPS_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0h Reserved
7cfg_lps_pwr_mode_7R/WMC,00h Reserved
6cfg_lps_pwr_mode_6R/WMC,00h Reserved
5cfg_lps_pwr_mode_5R/WMC,00h Reserved
4cfg_lps_pwr_mode_4R/WMC,00h Set to enter standby mode
3cfg_lps_pwr_mode_3R/WMC,00h Reserved
2cfg_lps_pwr_mode_2R/WMC,00h Reserved
1cfg_lps_pwr_mode_1R/WMC,00h Reserved
0cfg_lps_pwr_mode_0R/WMC,00h Set to enter normal mode

7.6.2.19 TDR_STATUS0 Register (Offset = 309h) [Reset = 0000h]

TDR_STATUS0 is shown in Figure 7-38 and described in Table 7-42.

Return to the Summary Table.

Figure 7-38 TDR_STATUS0 Register
15141312111098
peak1_loc
R-0h
76543210
peak0_loc
R-0h
Table 7-42 TDR_STATUS0 Register Field Descriptions
BitFieldTypeResetDescription
15-8peak1_locR0h Peak 1 location in tap index
7-0peak0_locR0h Peak 0 location in tap index

7.6.2.20 TDR_STATUS1 Register (Offset = 30Ah) [Reset = 0000h]

TDR_STATUS1 is shown in Figure 7-39 and described in Table 7-43.

Return to the Summary Table.

Figure 7-39 TDR_STATUS1 Register
15141312111098
peak3_loc
R-0h
76543210
peak2_loc
R-0h
Table 7-43 TDR_STATUS1 Register Field Descriptions
BitFieldTypeResetDescription
15-8peak3_locR0h Peak 3 location in tap index
7-0peak2_locR0h Peak 2 location in tap index

7.6.2.21 TDR_STATUS2 Register (Offset = 30Bh) [Reset = 0000h]

TDR_STATUS2 is shown in Figure 7-40 and described in Table 7-44.

Return to the Summary Table.

Figure 7-40 TDR_STATUS2 Register
15141312111098
peak0_amp
R-0h
76543210
peak4_loc
R-0h
Table 7-44 TDR_STATUS2 Register Field Descriptions
BitFieldTypeResetDescription
15-8peak0_ampR0h Peak 0 amplitude in echo coeff
7-0peak4_locR0h Peak 4 location in tap index

7.6.2.22 TDR_STATUS5 Register (Offset = 30Eh) [Reset = 0000h]

TDR_STATUS5 is shown in Figure 7-41 and described in Table 7-45.

Return to the Summary Table.

Figure 7-41 TDR_STATUS5 Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDpeak4_signpeak3_signpeak2_signpeak1_signpeak0_sign
R-0hR-0hR-0hR-0hR-0hR-0h
Table 7-45 TDR_STATUS5 Register Field Descriptions
BitFieldTypeResetDescription
15-5RESERVEDR0h Reserved
4peak4_signR0h Peak 4 sign
3peak3_signR0h Peak 3 sign
2peak2_signR0h Peak 2 sign
1peak1_signR0h Peak 1 sign
0peak0_signR0h Peak 0 sign

7.6.2.23 TDR_TC12 Register (Offset = 30Fh) [Reset = 0000h]

TDR_TC12 is shown in Figure 7-42 and described in Table 7-46.

Return to the Summary Table.

Figure 7-42 TDR_TC12 Register
15141312111098
RESERVEDfault_loc
R-0hR-0h
76543210
tdr_stateRESERVEDtdr_activation
R-0hR-0hR-0h
Table 7-46 TDR_TC12 Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0h Reserved
13-8fault_locR0h See TC12
7-4tdr_stateR0h See TC12
3-2RESERVEDR0h Reserved
1-0tdr_activationR0h See TC12

7.6.2.24 A2D_REG_05 Register (Offset = 405h) [Reset = 6400h]

A2D_REG_05 is shown in Figure 7-43 and described in Table 7-47.

Return to the Summary Table.

Figure 7-43 A2D_REG_05 Register
15141312111098
ld_bias_1p0v_slRESERVED
R/W-19hR/W-0h
76543210
RESERVED
R/W-0h
Table 7-47 A2D_REG_05 Register Field Descriptions
BitFieldTypeResetDescription
15-10ld_bias_1p0v_slR/W19h Bits to control the DAC current of LD and hence the swing.
001010b = 400 mV
001011b = 440 mV
001100b = 480 mV
001101b = 520 mV
001110b = 560 mV
001111b = 600 mV
010000b = 640 mV
010001b = 680 mV
010010b = 720 mV
010011b = 760 mV
010100b = 800 mV
010101b = 840 mV
010110b = 880 mV
010111b = 920 mV
011000b = 960 mV
011001b = 1000 mV
011010b = 1040 mV
011011b = 1080 mV
011100b = 1120 mV
011101b = 1160 mV
011110b = 1200 mV
9-0RESERVEDR/W0h Reserved

7.6.2.25 A2D_REG_30 Register (Offset = 41Eh) [Reset = 0000h]

A2D_REG_30 is shown in Figure 7-44 and described in Table 7-48.

Return to the Summary Table.

Figure 7-44 A2D_REG_30 Register
15141312111098
RESERVEDspare_in_2_fromdig_sl_force_en
R-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-48 A2D_REG_30 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0h Reserved
8spare_in_2_fromdig_sl_force_enR/W0h Force control enable for Reg0x042F
7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5RESERVEDR/W0h Reserved
4RESERVEDR/W0h Reserved
3-0RESERVEDR/W0h Reserved

7.6.2.26 A2D_REG_31 Register (Offset = 41Fh) [Reset = 0000h]

A2D_REG_31 is shown in Figure 7-45 and described in Table 7-49.

Return to the Summary Table.

Figure 7-45 A2D_REG_31 Register
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-49 A2D_REG_31 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10-7RESERVEDR/W0h Reserved
6-3RESERVEDR/W0h Reserved
2RESERVEDR/W0h Reserved
1RESERVEDR/W0h Reserved
0RESERVEDR/W0h Reserved

7.6.2.27 A2D_REG_40 Register (Offset = 428h) [Reset = 6002h]

A2D_REG_40 is shown in Figure 7-46 and described in Table 7-50.

Return to the Summary Table.

Figure 7-46 A2D_REG_40 Register
15141312111098
RESERVEDSGMII_TESTMODERESERVEDSGMII_SOP_SON_SLEW_CTRLRESERVEDRESERVED
R/W-0hR/W-3hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVED
R/W-0hR/W-1hR/W-0h
Table 7-50 A2D_REG_40 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14-13SGMII_TESTMODER/W3h 00b = 1000mV Sgmii output swing
01b = 1260mV Sgmii output swing
10b = 900mV Sgmii output swing
11b = 720mV Sgmii output swing
12RESERVEDR/W0h Reserved
11SGMII_SOP_SON_SLEW_CTRLR/W0h 0b =Default output rise/fall time
1b = Slow output rise/fall time
10RESERVEDR/W0h Reserved
9-8RESERVEDR/W0h Reserved
7RESERVEDR/W0h Reserved
6-1RESERVEDR/W1h Reserved
0RESERVEDR/W0h Reserved

7.6.2.28 A2D_REG_41 Register (Offset = 429h) [Reset = 0030h]

A2D_REG_41 is shown in Figure 7-47 and described in Table 7-51.

Return to the Summary Table.

Figure 7-47 A2D_REG_41 Register
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDSGMII_IO_LOOPBACK_ENRESERVED
R/W-ChR/W-0hR/W-0h
Table 7-51 A2D_REG_41 Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9RESERVEDR/W0h Reserved
8RESERVEDR/W0h Reserved
7-2RESERVEDR/WCh Reserved
1SGMII_IO_LOOPBACK_ENR/W0h 1b = Connects RX and TX signals internally to provide internal loopback option without external components.
0RESERVEDR/W0h Reserved

7.6.2.29 A2D_REG_43 Register (Offset = 42Bh) [Reset = 0000h]

A2D_REG_43 is shown in Figure 7-48 and described in Table 7-52.

Return to the Summary Table.

Figure 7-48 A2D_REG_43 Register
15141312111098
SGMII_CDR_TESTMODE_1
R/W-0h
76543210
SGMII_CDR_TESTMODE_1
R/W-0h
Table 7-52 A2D_REG_43 Register Field Descriptions
BitFieldTypeResetDescription
15-0SGMII_CDR_TESTMODE_1R/W0h SGMII RX CDR test mode

7.6.2.30 A2D_REG_44 Register (Offset = 42Ch) [Reset = 0000h]

A2D_REG_44 is shown in Figure 7-49 and described in Table 7-53.

Return to the Summary Table.

Figure 7-49 A2D_REG_44 Register
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDSGMII_DIG_LOOPBACK_ENRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-53 A2D_REG_44 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9RESERVEDR/W0h Reserved
8RESERVEDR/W0h Reserved
7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5RESERVEDR/W0h Reserved
4SGMII_DIG_LOOPBACK_ENR/W0h 1b = Loops back TX data to RX before the IO
3-1RESERVEDR/W0h Reserved
0RESERVEDR/W0h Reserved

7.6.2.31 A2D_REG_46 Register (Offset = 42Eh) [Reset = 0000h]

A2D_REG_46 is shown in Figure 7-50 and described in Table 7-54.

Return to the Summary Table.

Figure 7-50 A2D_REG_46 Register
15141312111098
RESERVEDsgmii_calib_watchdog_dissgmii_calib_watchdog_valsgmii_calib_avg
R-0hR/W-0hR/W-0hR/W-0h
76543210
sgmii_calib_avgsgmii_do_calibSGMII_CDR_LOCK_SLSGMII_MODE_force_enSGMII_INPUT_TERM_EN_force_enSGMII_OUTPUT_EN_force_enSGMII_COMP_OFFSET_TUNE_force_enSGMII_DATA_SYNC_SL
R/W-0hR/WSC-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0h
Table 7-54 A2D_REG_46 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0h Reserved
11sgmii_calib_watchdog_disR/W0h By default, SGMII calibration process has a watchdog timer. If calibration is not ended till timer expires, then it is dsabled and default value is taken. If this bit is set, then the calibration watchdog timer is disabled.
10-9sgmii_calib_watchdog_valR/W0h Watchdog timer configuration for SGMII calibration sequence: 00 - If not ended, calibration stops after 32us 01 - If not ended, calibration stops after 48us 10 - If not ended, calibration stops after 64us 11 - If not ended, calibration stops after 128us
8-7sgmii_calib_avgR/W0h Number of repetitions of COMP_OFFSET_TUNE calibration (the repetitions are for averaging): 00 - a single repetition 01 - 2 repetitions 10 - 4 repetitions 11 - 8 repetitions
6sgmii_do_calibR/WSC0h SGMII start calibration command (mainly for debug) Please notice: This register is WSC (write-self-clear) and not read-only!
5SGMII_CDR_LOCK_SLR0h Indicates Sgmiis CDR lock status
4SGMII_MODE_force_enR/W0h
3SGMII_INPUT_TERM_EN_force_enR/W0h
2SGMII_OUTPUT_EN_force_enR/W0h
1SGMII_COMP_OFFSET_TUNE_force_enR/W0h
0SGMII_DATA_SYNC_SLR0h

7.6.2.32 A2D_REG_47 Register (Offset = 42Fh) [Reset = 0000h]

A2D_REG_47 is shown in Figure 7-51 and described in Table 7-55.

Return to the Summary Table.

Figure 7-51 A2D_REG_47 Register
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDRESERVEDspare_in_2_fromdig_sl_2spare_in_2_fromdig_sl_1spare_in_2_fromdig_sl_0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-55 A2D_REG_47 Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR/W0h Reserved
3RESERVEDR/W0h Reserved
2spare_in_2_fromdig_sl_2R/W0h energy lost indication force control value
1spare_in_2_fromdig_sl_1R/W0h energy lost detector enable force control value
0spare_in_2_fromdig_sl_0R/W0h [0] - sleep enable force control value Force control enable is controlled by reg0x041E[8]

7.6.2.33 A2D_REG_48 Register (Offset = 430h) [Reset = 0960h]

A2D_REG_48 is shown in Figure 7-52 and described in Table 7-56.

Return to the Summary Table.

Figure 7-52 A2D_REG_48 Register
15141312111098
RESERVEDRESERVEDRESERVEDDLL_ENDLL_TX_DELAY_CTRL_SL
R-0hR/W-0hR/W-0hR/W-0hR/W-9h
76543210
DLL_RX_DELAY_CTRL_SLRESERVED
R/W-6hR/W-0h
Table 7-56 A2D_REG_48 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12DLL_ENR/W0h
11-8DLL_TX_DELAY_CTRL_SLR/W9h Refer to electrical specification for delay vs code information.
7-4DLL_RX_DELAY_CTRL_SLR/W6h Refer to electrical specification for delay vs code information.
3-0RESERVEDR/W0h Reserved

7.6.2.34 A2D_REG_66 Register (Offset = 442h) [Reset = 0000h]

A2D_REG_66 is shown in Figure 7-53 and described in Table 7-57.

Return to the Summary Table.

Figure 7-53 A2D_REG_66 Register
15141312111098
RESERVEDesd_event_countRESERVED
R/W-0hR-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0h
Table 7-57 A2D_REG_66 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14-9esd_event_countR0h Number gives the number of esd events on the copper channel
8RESERVEDR/W0h Reserved
7-5RESERVEDR/W0h Reserved
4RESERVEDR/W0h Reserved
3-0RESERVEDR/W0h Reserved

7.6.2.35 LEDS_CFG_1 Register (Offset = 450h) [Reset = 2610h]

LEDS_CFG_1 is shown in Figure 7-54 and described in Table 7-58.

Return to the Summary Table.

Figure 7-54 LEDS_CFG_1 Register
15141312111098
RESERVEDleds_bypass_stretchingleds_blink_rateled_2_option
R-0hR/W-0hR/W-2hR/W-6h
76543210
led_1_optionled_0_option
R/W-1hR/W-0h
Table 7-58 LEDS_CFG_1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h
14leds_bypass_stretchingR/W0h LED Signal Stretch
11-8led_2_optionR/W6h 0000b = link OK
0001b = link OK + blink on TX/RX activity
0010b = link OK + blink on TX activity
0011b = link OK + blink on RX activity
0100b = link OK + 100Base-T1 Master
0101b = link OK + 100Base-T1 Slave
0110b = TX/RX activity with stretch option
0111b = Reserved
1000b = Reserved
1001b = Link lost (remains on until register 0x1 is read)
1010b = PRBS error latch until cleared by 0x620(1)
1011b = XMII TX/RX Error with stretch option
7-4led_1_optionR/W1h 0000b = link OK
0001b = link OK + blink on TX/RX activity
0010b = link OK + blink on TX activity
0011b = link OK + blink on RX activity
0100b = link OK + 100Base-T1 Master
0101b = link OK + 100Base-T1 Slave
0110b = TX/RX activity with stretch option
0111b = Reserved
1000b = Reserved
1001b = Link lost (remains on until register 0x1 is read)
1010b = PRBS error (latch until cleared by 0x620(1)
1011b = XMII TX/RX Error with stretch option
3-0led_0_optionR/W0h 0000b = link OK
0001b = link OK + blink on TX/RX activity
0010b = link OK + blink on TX activity
0011b = link OK + blink on RX activity
0100b = link OK + 100Base-T1 Master
0101b = link OK + 100Base-T1 Slave
0110b = TX/RX activity with stretch option
0111b = Reserved
1000b = Reserved
1001b = Link lost (remains on until register 0x1 is read)
1010b = PRBS error (latch until cleared by 0x620(1)
1011b = XMII TX/RX Error with stretch option

7.6.2.36 LEDS_CFG_2 Register (Offset = 451h) [Reset = 0000h]

LEDS_CFG_2 is shown in Figure 7-55 and described in Table 7-59.

Return to the Summary Table.

Figure 7-55 LEDS_CFG_2 Register
15141312111098
RESERVEDRESERVEDXXXXled_2_drv_en
R-0hR-0h R/W-0h
76543210
led_2_drv_valled_2_polarityled_1_drv_enled_1_drv_valled_1_polarityled_0_drv_enled_0_drv_valled_0_polarity
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-59 LEDS_CFG_2 Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0h Reserved
13-10RESERVEDR0h Reserved
11-9cfg_ieee_compl_selR/W0h Observe IEEE Compliance signals in LED_0_GPIO_0, when LED_0_GPIO_CTRL= 'h5 as follows -
000b = loc_rcvr_status
001b = rem_rcvr_status
010b = loc_snr_margin
011b = rem_phy_ready
100b = pma_watchdog_status
101b = link_sync_link_control
8led_2_drv_enR/W0h LED_2 Drive Enable, When set, drives the value as per LED_2_DRV_VAL
7led_2_drv_valR/W0h LED_2 Drive Value, when LED_2_DRV_EN is set
6led_2_polarityR/W0h LED_2 polarity
5led_1_drv_enR/W0h LED_1 Drive Enable, When set, drives the value as per LED_1_DRV_VAL
4led_1_drv_valR/W0h LED_1 Drive Value, when LED_1_DRV_EN is set
3led_1_polarityR/W0h LED_1 polarity
2led_0_drv_enR/W0h LED_0 Drive Enable, When set, drives the value as per LED_0_DRV_VAL
1led_0_drv_valR/W0h LED_0 Drive Value, when LED_0_DRV_EN is set
0led_0_polarityR/W0h LED_0 polarity

7.6.2.37 IO_MUX_CFG_1 Register (Offset = 452h) [Reset = 0000h]

IO_MUX_CFG_1 is shown in Figure 7-56 and described in Table 7-60.

Return to the Summary Table.

Figure 7-56 IO_MUX_CFG_1 Register
15141312111098
RESERVEDRESERVEDled_1_gpio_ctrl
R-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDled_0_gpio_ctrl
R-0hR/W-0hR/W-0h
Table 7-60 IO_MUX_CFG_1 Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0h Reserved
13-11RESERVEDR/W0h Reserved
10-8led_1_gpio_ctrlR/W0h Controls the output of LED_1 IO -
000b = LED_1 (default: link OK + blink on TX/RX activity)
001b = Reserved
010b = RGMII data match indication
011b = Under-Voltage indication
100b = Interrupt
101b = IEEE compliance signals
110b = constant 0
111b = constant 1
7-6RESERVEDR0h Reserved
5-3RESERVEDR/W0h Reserved
2-0led_0_gpio_ctrlR/W0h Controls the output of LED_0 IO:
000b = LED_0 (default: LINK)
001b = Reserved
010b = RGMII data match indication
011b = Under-Voltage indication
100b = Interrupt
101b = IEEE compliance signals (see 0x451[11:9])
110b = constant 0
111b = constant 1

7.6.2.38 IO_MUX_CFG_2 Register (Offset = 453h) [Reset = 0001h]

IO_MUX_CFG_2 is shown in Figure 7-57 and described in Table 7-61.

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Figure 7-57 IO_MUX_CFG_2 Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDclk_o_clk_sourceclk_o_gpio_ctrl
R-0hR/W-0hR/W-1h
Table 7-61 IO_MUX_CFG_2 Register Field Descriptions
BitFieldTypeResetDescription
15-6RESERVEDR0h Reserved
5-3clk_o_clk_sourceR/W0h Clock Observable in CLK_O pin -
000b = xi_osc_25m_1p0v_dl (25MHz crystal output - from analog)
001b = Reserved
010b = Reserved
011b = 125MHz clock
100b = 125MHz clock
101b = Reserved
110b = Reserved
111b = Reserved
2-0clk_o_gpio_ctrlR/W1h Controls the output of CLK_O IO -
000b = LED_2 (default: TX/RX activity with stretch
option(LED_2_OPTION=0x6) 001b = Clock out (see 0x453[5:3])
010b = RGMII data match indication
011b = Under-Voltage indication
100b = constant 0
101b = constant 0
110b = constant 0
111b = constant 1

7.6.2.39 IO_CONTROL_1 Register (Offset = 454h) [Reset = 0000h]

IO_CONTROL_1 is shown in Figure 7-58 and described in Table 7-62.

Return to the Summary Table.

Figure 7-58 IO_CONTROL_1 Register
15141312111098
io_control_1
R/W-0h
76543210
io_control_1
R/W-0h
Table 7-62 IO_CONTROL_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0io_control_1R/W0h IO_CONTROL_1 : IO reflects the value written on this register when enabled IO_OE_N_FORCE_CTRL=1 and IO_OE_N_VALUE=0
If 0 is written, IO will be forced to ouput LOW.
If 1 is written, IO will be forced to ouput HIGH. The following is the bit position for pads.
0=LED_0_GPIO_0;
1=LED_1_GPIO_1;
2=CLKOUT_GPIO_2;
3=INT_N;
4=RESERVED;
5=RESERVED;
6=INH;
7=TX_CLK;
8=TX_CTRL;
9=TX_D0;
10=TX_D1;
11=TX_D2;
12=TX_D3;
13=RX_CLK;
14=RX_CTRL;
15=RX_D0;

7.6.2.40 IO_CONTROL_2 Register (Offset = 455h) [Reset = 0000h]

IO_CONTROL_2 is shown in Figure 7-59 and described in Table 7-63.

Return to the Summary Table.

Figure 7-59 IO_CONTROL_2 Register
15141312111098
RESERVEDcfg_other_impedancepupd_value
R-0hR/W-0hR/W-0h
76543210
pupd_valuepupd_force_cntlio_oe_n_valueio_oe_n_force_ctrlio_control_2
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-63 IO_CONTROL_2 Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0h Reserved
13-9cfg_other_impedanceR/W0h Slew Rate Control for CLKOUT -
00000b = Default rise/fall time
00001b = Slower rise/fall time
00010b = Faster rise/fall time
8-7pupd_valueR/W0h IO Test mode - pullup/pull down :
00b = No pull (HiZ)
01b = PullUP
10b = PullDown
11b = PullUp/PullDown (Both Enabled)
6pupd_force_cntlR/W0h IO Test mode pull up/down override functional pull.
5io_oe_n_valueR/W0h IO Test mode direction, related to IO_OE_N_FORCE_CTRL
4io_oe_n_force_ctrlR/W0h IO Test mode (alternate to BSR). The IO direction is set by IO_OE_N_VALUE and value is set by IO_CONTROL_1/2
3-0io_control_2R/W0h IO_CONTROL_2 : IO reflects the value written on this register when enabled IO_OE_N_FORCE_CTRL=1 and IO_OE_N_VALUE=0 If 0 is written, IO will be forced to ouput LOW.
If 1 is written, IO will be forced to ouput HIGH. The following is the bit position for pads.
0=RX_D1;
1=RX_D2;
2=RX_D3;
3=STRP_1;

7.6.2.41 IO_CONTROL_3 Register (Offset = 456h) [Reset = 0108h]

IO_CONTROL_3 is shown in Figure 7-60 and described in Table 7-64.

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Figure 7-60 IO_CONTROL_3 Register
15141312111098
RESERVEDcfg_mac_rx_impedance
R-0hR/W-8h
76543210
cfg_mac_rx_impedanceRESERVED
R/W-8hR/W-8h
Table 7-64 IO_CONTROL_3 Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0h Reserved
9-5cfg_mac_rx_impedanceR/W8h Slew Rate Control for RGMII pads -
01010b = Medium Slew (OA tr/tf compliant, max tr/tf = 1ns)
01011b = Slowest Slew (For low emissions, max tr/tf = 1.2ns)
01000b = Default mode (rgmii tr/tf compliant, max tr/tf=750ps)
4-0RESERVEDR/W8h Reserved

7.6.2.42 IO_STATUS_1 Register (Offset = 457h) [Reset = 0000h]

IO_STATUS_1 is shown in Figure 7-61 and described in Table 7-65.

Return to the Summary Table.

Figure 7-61 IO_STATUS_1 Register
15141312111098
io_status_1
R-0h
76543210
io_status_1
R-0h
Table 7-65 IO_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0io_status_1R0h IO_STATUS_1 : Register reflects the IO value, when enabled IO_OE_N_FORCE_CTRL=1 and IO_OE_N_VALUE=1 If 0 is read, IO is connected LOW at pin.
If 1 is read, IO is connected HIGH at pin.
The following is the bit position for each pad.
0=LED_0_GPIO_0;
1=LED_1_GPIO_1;
2=CLKOUT_GPIO_2;
3=INT_N;
4=RESERVED;
5=RESERVED;
6=INH;
7=TX_CLK;
8=TX_CTRL;
9=TX_D0;
10=TX_D1;
11=TX_D2;
12=TX_D3;
13=RX_CLK;
14=RX_CTRL;
15=RX_D0;

7.6.2.43 IO_STATUS_2 Register (Offset = 458h) [Reset = 0000h]

IO_STATUS_2 is shown in Figure 7-62 and described in Table 7-66.

Return to the Summary Table.

Figure 7-62 IO_STATUS_2 Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDio_status_2
R-0hR-0h
Table 7-66 IO_STATUS_2 Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR0h
3-0io_status_2R0h IO_STATUS_2 : Register reflects the IO value, when enabled IO_OE_N_FORCE_CTRL=1 and IO_OE_N_VALUE=1 If 0 is read, IO is connected LOW at pin.
If 1 is read, IO is connected HIGH at pin.
The following is the bit position for each pad.
0=RX_D1;
1=RX_D2;
2=RX_D3;
3=STRP_1;

7.6.2.44 IO_CONTROL_4 Register (Offset = 459h) [Reset = 0000h]

IO_CONTROL_4 is shown in Figure 7-63 and described in Table 7-67.

Return to the Summary Table.

Figure 7-63 IO_CONTROL_4 Register
15141312111098
io_input_mode
R/W-0h
76543210
io_input_mode
R/W-0h
Table 7-67 IO_CONTROL_4 Register Field Descriptions
BitFieldTypeResetDescription
15-0io_input_modeR/W0h Each bit configures one pin into input mode as per mapping below -
0=LED_0_GPIO_0;
1=LED_1_GPIO_1;
2=CLKOUT_GPIO_2;
3=INT_N;
4=TX_CLK;
5=TX_CTRL;
6=TX_D0;
7=TX_D1;
8=TX_D2;
9=TX_D3;
10=RX_CLK;
11=RX_CTRL;
12=RX_D0;
13=RX_D1;
14=RX_D2;
15=RX_D3

7.6.2.45 IO_CONTROL_5 Register (Offset = 45Ah) [Reset = 0000h]

IO_CONTROL_5 is shown in Figure 7-64 and described in Table 7-68.

Return to the Summary Table.

Figure 7-64 IO_CONTROL_5 Register
15141312111098
io_output_mode
R/W-0h
76543210
io_output_mode
R/W-0h
Table 7-68 IO_CONTROL_5 Register Field Descriptions
BitFieldTypeResetDescription
15-0io_output_modeR/W0h Each bit configures one pin into output mode as per mapping below -
0=LED_0_GPIO_0;
1=LED_1_GPIO_1;
2=CLKOUT_GPIO_2;
3=INT_N;
4=TX_CLK;
5=TX_CTRL;
6=TX_D0;
7=TX_D1;
8=TX_D2;
9=TX_D3;
10=RX_CLK;
11=RX_CTRL;
12=RX_D0;
13=RX_D1;
14=RX_D2;
15=RX_D3

7.6.2.46 SOR_VECTOR_1 Register (Offset = 45Dh) [Reset = 0000h]

SOR_VECTOR_1 is shown in Figure 7-65 and described in Table 7-69.

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Figure 7-65 SOR_VECTOR_1 Register
15141312111098
RGMII_TX_SHIFTRGMII_RX_SHIFTSGMII_ENRGMII_ENTEST_MODEMAC_MODE
R-0hR-0hR-0hR-0hR-0hR-0h
76543210
MAC_MODEMAS/SLVPHY_AD
R-0hR-0hR-0h
Table 7-69 SOR_VECTOR_1 Register Field Descriptions
BitFieldTypeResetDescription
15RGMII_TX_SHIFTR0h 0x0 = TX shift disbaled
0x1 = TX shift enabled
14RGMII_RX_SHIFTR0h 0x0 = RX shift disabled
0x1 = RX shift enabled
13SGMII_ENR0h 0x0 = SGMII disabled
0x1 = SGMII enabled
12RGMII_ENR0h 0x0 = RGMII disabled
0x1 = RGMII enabled
11-9TEST_MODER0h
8-6MAC_MODER0h 0x0 = SGMII
0x1 = Reserved
0x2 = Reserved
0x3 = Reserved
0x4 = RGMII align
0x5 = RGMII TX shift
0x6 = RGMII TX and RX shift
0x7 = RGMII RX shift
5MAS/SLVR0h 0x0 = Slave
0x1 = Master
4-0PHY_ADR0h 0x0 = PHY address 0
0x4 = PHY address 4
0x5 = PHY address 5
0x8 = PHY address 8
0xA = PHY address A
0xC = PHY address C
0xD = PHY address D
0xE = PHY address E
0xF = PHY address F

7.6.2.47 SOR_VECTOR_2 Register (Offset = 45Eh) [Reset = 0000h]

SOR_VECTOR_2 is shown in Figure 7-66 and described in Table 7-70.

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Figure 7-66 SOR_VECTOR_2 Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDAUTO/MANAGED
R-0hR-0h
Table 7-70 SOR_VECTOR_2 Register Field Descriptions
BitFieldTypeResetDescription
15-1RESERVEDR0h Reserved
0AUTO/MANAGEDR0h 0x0 = Autonomous mode enabled 0x1 = Managed mode enabled

7.6.2.48 MONITOR_CTRL1 Register (Offset = 467h) [Reset = 0012h]

MONITOR_CTRL1 is shown in Figure 7-67 and described in Table 7-71.

Return to the Summary Table.

Figure 7-67 MONITOR_CTRL1 Register
15141312111098
cfg_dc_offset_2c
R/W-0h
76543210
cfg_cic_gain12_arithcfg_cic_gain2cfg_cic_gain1
R/W-0hR/W-2hR/W-2h
Table 7-71 MONITOR_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
15-8cfg_dc_offset_2cR/W0h Analog control
7-6cfg_cic_gain12_arithR/W0h Analog control
5-3cfg_cic_gain2R/W2h Analog control
2-0cfg_cic_gain1R/W2h Analog control

7.6.2.49 MONITOR_CTRL2 Register (Offset = 468h) [Reset = 0920h]

MONITOR_CTRL2 is shown in Figure 7-68 and described in Table 7-72.

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Figure 7-68 MONITOR_CTRL2 Register
15141312111098
cfg_bypass_reset_sensor_valcfg_rd_datacfg_dec_factor_sensorscfg_dec_factor_gain_calib
R/W-0hR/W-0hR/W-4hR/W-4h
76543210
cfg_dec_factor_gain_calibcfg_dec_factor_dc_calibcfg_bypass_sel_num
R/W-4hR/W-4hR/W-0h
Table 7-72 MONITOR_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
15cfg_bypass_reset_sensor_valR/W0h When cfg_bypass_fsm is 1, use this register to keep sensor in reset
14-12cfg_rd_dataR/W0h To read out monitor adc output through MDIO for debug
11-9cfg_dec_factor_sensorsR/W4h Analog control
8-6cfg_dec_factor_gain_calibR/W4h Analog control
5-3cfg_dec_factor_dc_calibR/W4h Analog control
2-0cfg_bypass_sel_numR/W0h When cfg_bypass_fsm is 1, use this register to select the sensor

7.6.2.50 MONITOR_CTRL4 Register (Offset = 46Ah) [Reset = 0094h]

MONITOR_CTRL4 is shown in Figure 7-69 and described in Table 7-73.

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Figure 7-69 MONITOR_CTRL4 Register
15141312111098
RESERVEDcfg_hist_clr
R-0hR/W-0h
76543210
cfg_discard_sample_numcfg_avg_sample_numcfg_adc_clk_divcfg_force_startcfg_resetperiodicstart
R/W-1hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/WSC-0h
Table 7-73 MONITOR_CTRL4 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0h RESERVED
8cfg_hist_clrR/W0h CFG_HIST_CLR
7cfg_discard_sample_numR/W1h Number of samples to be discarded before starting averaging - 0b = 2 samples 1b = 4 samples
6cfg_avg_sample_numR/W0h Number of samples for calculating the average before storing in history - 0b = 2 samples 1b = 4 samples
5-4cfg_adc_clk_divR/W1h Config options to select frequency of monitor adc clock - 00b = 12.5MHz 01b = 6.25MHz 10b = 3.125MHz 11b = Reserved
3cfg_force_startR/W0h Set to force start sensor monitor FSM even if link is not established
2cfg_resetR/W1h 0b = Enable the monitor 1b = Monitor is held in reset state At any point of time, if the signal is changed to 1, the module abruptly goes to reset state
1periodicR/W0h 0b = Monitor is enabled only when start is set for one iteration 1b = Monitor is enabled for periodic iteration
0startR/WSC0h Start indication for sensor monitor FSM, self clearing

7.6.2.51 MONITOR_STAT1 Register (Offset = 47Bh) [Reset = 0000h]

MONITOR_STAT1 is shown in Figure 7-70 and described in Table 7-74.

Return to the Summary Table.

Figure 7-70 MONITOR_STAT1 Register
15141312111098
stat_rd_data
R-0h
76543210
stat_rd_data
R-0h
Table 7-74 MONITOR_STAT1 Register Field Descriptions
BitFieldTypeResetDescription
15-0stat_rd_dataR0h STAT_RD_DATA

BREAK_LINK_TIMER is shown in Figure 7-71 and described in Table 7-75.

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Figure 7-71 BREAK_LINK_TIMER Register
Table 7-75 BREAK_LINK_TIMER Register Field Descriptions

7.6.2.53 RS_DECODER Register (Offset = 510h) [Reset = 2D50h]

RS_DECODER is shown in Figure 7-72 and described in Table 7-76.

Return to the Summary Table.

Figure 7-72 RS_DECODER Register
15141312111098
cfg_rs_decoder_bypassRESERVEDRESERVED
R/W-0hR/W-0hR/W-2Dh
76543210
RESERVEDRESERVED
R/W-28hR/W-0h
Table 7-76 RS_DECODER Register Field Descriptions
BitFieldTypeResetDescription
15cfg_rs_decoder_bypassR/W0h Bypass RS decoder
0h = RS decoder in use
1h = Bypass RS decoder
14RESERVEDR/W0h Reserved
13-8RESERVEDR/W2Dh Reserved
7-1RESERVEDR/W28h Reserved
0RESERVEDR/W0h Reserved

7.6.2.54 LPS_CONTROL_1 Register (Offset = 514h) [Reset = 08E3h]

LPS_CONTROL_1 is shown in Figure 7-73 and described in Table 7-77.

Return to the Summary Table.

Figure 7-73 LPS_CONTROL_1 Register
15141312111098
RESERVEDcfg_tx_wake_cgcfg_tx_sleep_cg
R-0hR/W-4hR/W-3h
76543210
cfg_tx_sleep_cgcfg_rx_wake_cgcfg_rx_sleep_cg
R/W-3hR/W-4hR/W-3h
Table 7-77 LPS_CONTROL_1 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0h Reserved
11-9cfg_tx_wake_cgR/W4h Control code to send on Tx for wake indication
8-6cfg_tx_sleep_cgR/W3h Control code to send on Tx for sleep indication
5-3cfg_rx_wake_cgR/W4h Control code to expect on Rx for wake indication
2-0cfg_rx_sleep_cgR/W3h Control code to expect on Rx for sleep indication

7.6.2.55 LPS_CONTROL_2 Register (Offset = 515h) [Reset = 0808h]

LPS_CONTROL_2 is shown in Figure 7-74 and described in Table 7-78.

Return to the Summary Table.

Figure 7-74 LPS_CONTROL_2 Register
15141312111098
RESERVEDcfg_wake_cg_cnt_th
R-0hR/W-8h
76543210
RESERVEDcfg_sleep_cg_cnt_th
R-0hR/W-8h
Table 7-78 LPS_CONTROL_2 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14-8cfg_wake_cg_cnt_thR/W8h Number of continuous expected wake code groups required to acknowledge and set LPS wake command received.
7RESERVEDR0h Reserved
6-0cfg_sleep_cg_cnt_thR/W8h Number of continuous expected sleep code groups required to acknowledge and set LPS sleep command received.

7.6.2.56 MAXWAIT_TIMER Register (Offset = 518h) [Reset = 17CEh]

MAXWAIT_TIMER is shown in Figure 7-75 and described in Table 7-79.

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Figure 7-75 MAXWAIT_TIMER Register
15141312111098
cfg_maxwait_timer_init
R/W-17CEh
76543210
cfg_maxwait_timer_init
R/W-17CEh
Table 7-79 MAXWAIT_TIMER Register Field Descriptions
BitFieldTypeResetDescription
15-0cfg_maxwait_timer_initR/W17CEh Maxwait timer (used during link-up) : value in us = decimal value multipled by 16

7.6.2.57 PHY_CTRL_1G Register (Offset = 519h) [Reset = 003Dh]

PHY_CTRL_1G is shown in Figure 7-76 and described in Table 7-80.

Return to the Summary Table.

Figure 7-76 PHY_CTRL_1G Register
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDcfg_force_link_stat_valcfg_force_link_statRESERVEDRESERVED
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
cfg_minwait_timer_init
R/W-3Dh
Table 7-80 PHY_CTRL_1G Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
9RESERVEDR/W0h Reserved
8RESERVEDR/W0h Reserved
7-0cfg_minwait_timer_initR/W3Dh Minwait timer (used during link-up) : value in us = decimal value multipled by 16

7.6.2.58 TEST_MODE Register (Offset = 531h) [Reset = 0000h]

TEST_MODE is shown in Figure 7-77 and described in Table 7-81.

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Figure 7-77 TEST_MODE Register
15141312111098
RESERVEDcfg_test_mode4_tx_order
R-0hR/W-0h
76543210
cfg_test_mode_7_data
R/W-0h
Table 7-81 TEST_MODE Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0h Reserved
8cfg_test_mode4_tx_orderR/W0h Order of symbols to be transmitted in Test mode 4
0h = T1 followed by T2
1h = T2 followed by T1
7-0cfg_test_mode_7_dataR/W0h GMII data to transmit in Test mode 7

LINK_QUAL_1 is shown in Figure 7-78 and described in Table 7-82.

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Figure 7-78 LINK_QUAL_1 Register
Table 7-82 LINK_QUAL_1 Register Field Descriptions

LINK_QUAL_2 is shown in Figure 7-79 and described in Table 7-83.

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Figure 7-79 LINK_QUAL_2 Register
Table 7-83 LINK_QUAL_2 Register Field Descriptions

LINK_DOWN_LATCH_STAT is shown in Figure 7-80 and described in Table 7-84.

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Figure 7-80 LINK_DOWN_LATCH_STAT Register
Table 7-84 LINK_DOWN_LATCH_STAT Register Field Descriptions

LINK_QUAL_3 is shown in Figure 7-81 and described in Table 7-85.

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Figure 7-81 LINK_QUAL_3 Register
Table 7-85 LINK_QUAL_3 Register Field Descriptions

LINK_QUAL_4 is shown in Figure 7-82 and described in Table 7-86.

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Figure 7-82 LINK_QUAL_4 Register
Table 7-86 LINK_QUAL_4 Register Field Descriptions

7.6.2.64 RS_DECODER_FRAME_STAT_2 Register (Offset = 552h) [Reset = 0000h]

RS_DECODER_FRAME_STAT_2 is shown in Figure 7-83 and described in Table 7-87.

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Figure 7-83 RS_DECODER_FRAME_STAT_2 Register
15141312111098
rs_dec_uncorr_frame_cnt
0h
76543210
rs_dec_uncorr_frame_cnt
0h
Table 7-87 RS_DECODER_FRAME_STAT_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0rs_dec_uncorr_frame_cnt0h No of uncorrectable RS frames received at RS decoder, clear on read, saturates

7.6.2.65 PMA_WATCHDOG Register (Offset = 559h) [Reset = 0051h]

PMA_WATCHDOG is shown in Figure 7-84 and described in Table 7-88.

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Figure 7-84 PMA_WATCHDOG Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDcfg_pma_watchdog_force_valcfg_pma_watchdog_force_encfg_ieee_watchdog_encfg_watchdog_cnt_clr_th
R-0hR/W-1hR/W-0hR/W-1hR/W-1h
Table 7-88 PMA_WATCHDOG Register Field Descriptions
BitFieldTypeResetDescription
15-7RESERVEDR0h Reserved
6cfg_pma_watchdog_force_valR/W1h Force value for pma watchdog
5cfg_pma_watchdog_force_enR/W0h Enable forcing pma watchdog
4cfg_ieee_watchdog_enR/W1h 1 : watchdog counters are started after link up 0: TBD
3-0cfg_watchdog_cnt_clr_thR/W1h Number of 0, +1, -1 symbols to be seen in their respective watchdog counter window to prevent them for asserting pma_watchdog_status

7.6.2.66 SYMB_POL_CFG Register (Offset = 55Bh) [Reset = 0000h]

SYMB_POL_CFG is shown in Figure 7-85 and described in Table 7-89.

Return to the Summary Table.

Figure 7-85 SYMB_POL_CFG Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDcfg_slave_auto_pol_correction_encfg_rx_symb_order_invcfg_rx_symb_pol_invcfg_tx_symb_order_invcfg_tx_symb_pol_inv
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-89 SYMB_POL_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-5RESERVEDR0h Reserved
4cfg_slave_auto_pol_correction_enR/W0h Correct tx polarity for slave based on received polarity
0h = Slave tx polarity independent of slave rx polarity
1h = Slave tx polarity to match received polarity
3cfg_rx_symb_order_invR/W0h Order of received symbols S0 to S6 reversed to S6 to S0 Valid only if LPs 0x55B[1] is set (TI-TI link)
0h = Order of received symbols S0 to S6 unchanged
1h = Order of received symbols S0 to S6 reversed to S6 to S0
2cfg_rx_symb_pol_invR/W0h Invert polarity of received symbols
0h = Unchanged polarity of received symbols
1h = Invert polarity of received symbols
1cfg_tx_symb_order_invR/W0h Order of transmit symbols S0 to S6 reversed to S6 to S0 Valid only if LPs 0x55B[3] is set (TI-TI link)
0h = Order of transmit symbols S0 to S6 unchanged
1h = Order of transmit symbols S0 to S6 reversed to S6 to S0
0cfg_tx_symb_pol_invR/W0h Invert polarity of transmit symbols
0h = Unchanged polarity of transmit symbols
1h = Invert polarity of transmit symbols

7.6.2.67 OAM_CFG Register (Offset = 55Ch) [Reset = 0000h]

OAM_CFG is shown in Figure 7-86 and described in Table 7-90.

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Figure 7-86 OAM_CFG Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDcfg_rx_oam_crc_data_in_ordercfg_tx_oam_crc_data_in_order
R-0hR/W-0hR/W-0h
Table 7-90 OAM_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0h Reserved
1cfg_rx_oam_crc_data_in_orderR/W0h Reverse order of data input to CRC checker in rx oam to MSB first
0h = Order of data input to CRC checker in rx oam is LSB first
1h = Order of data input to CRC checker in rx oam is MSB first
0cfg_tx_oam_crc_data_in_orderR/W0h Reverse order of data input to CRC calculator in tx oam to MSB first
0h = Order of data input to CRC calculator in tx oam is LSB first
1h = Order of data input to CRC calculator in tx oam is MSB first

7.6.2.68 TEST_MEM_CFG Register (Offset = 561h) [Reset = 17A0h]

TEST_MEM_CFG is shown in Figure 7-87 and described in Table 7-91.

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Figure 7-87 TEST_MEM_CFG Register
15141312111098
RESERVEDcfg_wait_time_xcorr_wen
R-0hR/W-5Eh
76543210
cfg_wait_time_xcorr_wencfg_xcorr_dbg_selcfg_send_s_infinite_loopcfg_xcorr_dbg_test_memcfg_ecc_encfg_test_mem_sigdet_debugcfg_pcs_test_mem_mode
R/W-5EhR/W-1hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-91 TEST_MEM_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h Reserved
12-6cfg_wait_time_xcorr_wenR/W5Eh Wait timer after TX_SEND_S after which testmem is written on energy fall Note : Valid only if 0x561[3] is set
5cfg_xcorr_dbg_selR/W1h 0b = Select xcorr from aligned detector to write to test mem 1b = Select xcorr from shifted detector to write to test mem Note : Valid only if 0x561[3] is set
4cfg_send_s_infinite_loopR/W0h enable transmitting infinite send_s sequence. For send_s debug. Valid only in master and when 0x56A[15] is set.
0h = disable infinte send_s mode
1h = enable infinite send_s mode
3cfg_xcorr_dbg_test_memR/W0h enabled xcorr debug for send_s. Valid only if 0x561[0] is 1b0
0h = Normal send_s debug. Refer to 0x561[1]
1h = Enabled xcorr debug
2cfg_ecc_enR/W0h Enable ECC logic for RS decoder memory
0h = ECC encoding/decoding is disabled
1h = ECC encoding/decoding is enabled
1cfg_test_mem_sigdet_debugR/W0h Enable sidget debug mode in test mem send s mode Valid only if 0x561[0] is 1b0
0h = Test mem written in send s mode only on state transition
1h = Enable sigdet debug mode in test mem send s mode
0cfg_pcs_test_mem_modeR/W0h Choose send s or train rx test mem mode
0h = Send s info on test mem
1h = Train rx info on test mem

7.6.2.69 FORCE_CTRL1 Register (Offset = 573h) [Reset = 0000h]

FORCE_CTRL1 is shown in Figure 7-88 and described in Table 7-92.

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Figure 7-88 FORCE_CTRL1 Register
15141312111098
RESERVEDcfg_force_link_sync_state_en
R-0hR/W-0h
76543210
cfg_force_link_sync_state_val
R/W-0h
Table 7-92 FORCE_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0h Reserved

7.6.2.70 RGMII_CTRL Register (Offset = 600h) [Reset = 0120h]

RGMII_CTRL is shown in Figure 7-89 and described in Table 7-93.

Return to the Summary Table.

Figure 7-89 RGMII_CTRL Register
15141312111098
RESERVEDrgmii_rx_half_full_th
R-0hR/W-2h
76543210
rgmii_rx_half_full_thrgmii_tx_half_full_thrgmii_tx_if_eninvert_rgmii_txdinvert_rgmii_rxdsup_tx_err_fd
R/W-2hR/W-2hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-93 RGMII_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0h Reserved
9-7rgmii_rx_half_full_thR/W2h RGMII RX sync FIFO half full threshold
6-4rgmii_tx_half_full_thR/W2h RGMII TX sync FIFO half full threshold
3rgmii_tx_if_enR/W0h RGMII enable bit Default from strap
0h = RGMII disable
1h = RGMII enable
2invert_rgmii_txdR/W0h Invert RGMII Tx wire order - full swap [3:0] to [0:3]
0h = Keep RGMII Tx wire order same - [3:
1h = Invert RGMII Tx wire order - [3:
1invert_rgmii_rxdR/W0h Invert RGMII Rx wire order - full swap [3:0] to [0:3]
0h = Keep RGMII Rx wire order same - [3:
1h = Invert RGMII Rx wire order - [3:
0sup_tx_err_fdR/W0h 1: suppress tx_err in full duplex mode when tx_en set to zero 0: allow tx_err assertion to PHY when tx_en set to zero (this bit can disable the TX_ERR indication input)

7.6.2.71 RGMII_FIFO_STATUS Register (Offset = 601h) [Reset = 0000h]

RGMII_FIFO_STATUS is shown in Figure 7-90 and described in Table 7-94.

Return to the Summary Table.

Figure 7-90 RGMII_FIFO_STATUS Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDrgmii_rx_af_full_errrgmii_rx_af_empty_errrgmii_tx_af_full_errrgmii_tx_af_empty_err
R-0hR/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0h
Table 7-94 RGMII_FIFO_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR0h Reserved
3rgmii_rx_af_full_errR/W0C0h RGMII RX fifo full error
0h = No empty fifo error
1h = RGMII TX full error has been indicated
2rgmii_rx_af_empty_errR/W0C0h RGMII RX fifo empty error
0h = No empty fifo error
1h = RGMII RX empty error has been indicated
1rgmii_tx_af_full_errR/W0C0h RGMII TX fifo full error
0h = No empty fifo error
1h = RGMII TX full error has been indicated
0rgmii_tx_af_empty_errR/W0C0h RGMII TX fifo empty error
0h = No empty fifo error
1h = RGMII TX empty error has been indicated

7.6.2.72 RGMII_DELAY_CTRL Register (Offset = 602h) [Reset = 0000h]

RGMII_DELAY_CTRL is shown in Figure 7-91 and described in Table 7-95.

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Figure 7-91 RGMII_DELAY_CTRL Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDrx_clk_seltx_clk_sel
R-0hR/W-0hR/W-0h
Table 7-95 RGMII_DELAY_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0h Reserved
1rx_clk_selR/W0h In RGMII mode, Enable or disable the internal delay for RXD wrt RX_CLK (use this mode when RGMII_RX_CLK and RGMII_RXD are aligned). The delay magnitude can be configured by programming register 0x430[7:4]
0h = clock and data are aligned
1h = clock on PIN is delayed by 90 degrees relative to RGMII_RX data
0tx_clk_selR/W0h In RGMII mode, Enable or disable the internal delay for TXD wrt TX_CLK (use this mode when RGMII_TX_CLK and RGMII_TXD are aligned). The delay magnitude can be configured by programming register 0x430[11:8]
0h = clock and data are aligned
1h = clock is internally delayed by 90 degrees

7.6.2.73 SGMII_CTRL_1 Register (Offset = 608h) [Reset = 007Bh]

SGMII_CTRL_1 is shown in Figure 7-92 and described in Table 7-96.

Return to the Summary Table.

Figure 7-92 SGMII_CTRL_1 Register
15141312111098
sgmii_tx_err_discfg_align_idx_forcecfg_align_idx_valuecfg_sgmii_encfg_sgmii_rx_pol_invert
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
cfg_sgmii_tx_pol_invertRESERVEDRESERVEDRESERVEDsgmii_autoneg_timermr_an_enable
R/W-0hR/W-3hR/W-1hR/W-1hR/W-1hR/W-1h
Table 7-96 SGMII_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15sgmii_tx_err_disR/W0h 1 = Disable SGMII TX Error indication
0 = Enable SGMII TX Error indication
14cfg_align_idx_forceR/W0h Force word boundray index selection
13-10cfg_align_idx_valueR/W0h when cfg_align_idx_force = 1 This value set the iword boundray index
9cfg_sgmii_enR/W0h SGMII enable bit Default from strap
0h = SGMII disable
1h = SGMII enable
8cfg_sgmii_rx_pol_invertR/W0h SGMII RX bus invert polarity
0h = Polarity not inverted
1h = SGMII RX bus invert polarity
7cfg_sgmii_tx_pol_invertR/W0h SGMII TX bus invert polarity
0h = Polarity not inverted
1h = SGMII TX bus invert polarity
6-5RESERVEDR/W3h Reserved
4RESERVEDR/W1h Reserved
3RESERVEDR/W1h Reserved
2-1sgmii_autoneg_timerR/W1h Selects duration of SGMII Auto-Negotiation timer: 00: 1.6ms 01: 2us 10: 800us 11: 11ms
0mr_an_enableR/W1h 1 = Enable SGMII Auto-Negotaition
0 = Disable SGMII Auto-Negotiation

7.6.2.74 SGMII_STATUS Register (Offset = 60Ah) [Reset = 0000h]

SGMII_STATUS is shown in Figure 7-93 and described in Table 7-97.

Return to the Summary Table.

Figure 7-93 SGMII_STATUS Register
15141312111098
RESERVEDsgmii_page_receivedlink_status_1000bxmr_an_completecfg_align_encfg_sync_status
R-0hR-0hR-0hR-0hR-0hR-0h
76543210
cfg_align_idxcfg_state
R-0hR-0h
Table 7-97 SGMII_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h Reserved
12sgmii_page_receivedR0h Indicates that a new auto neg page was received
0h = No new auto neg page received
1h = A new auto neg page received
10mr_an_completeR0h sgmii autoneg complete indication
0h = SGMII autoneg not completed
1h = SGMII autoneg completed
9cfg_align_enR0h word boundary FSM - align indication
8cfg_sync_statusR0h word boundary FSM - sync status indication
0h = sync not achieved
1h = sync achieved
7-4cfg_align_idxR0h word boundary index selection
3-0cfg_stateR0h word boundary FSM state

7.6.2.75 SGMII_CTRL_2 Register (Offset = 60Ch) [Reset = 001Bh]

SGMII_CTRL_2 is shown in Figure 7-94 and described in Table 7-98.

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Figure 7-94 SGMII_CTRL_2 Register
15141312111098
RESERVEDsgmii_signal_detect_force_val
R-0hR/W-0h
76543210
sgmii_signal_detect_force_enmr_restart_antx_half_full_thrx_half_full_th
R/W-0hR/WSC,0-0hR/W-3hR/W-3h
Table 7-98 SGMII_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0h Reserved
8sgmii_signal_detect_force_valR/W0h SGMII cdr lock force value
7sgmii_signal_detect_force_enR/W0h SGMII cdr lock force enable
6mr_restart_anR/WSC,00h Restart sgmii autonegotiation
5-3tx_half_full_thR/W3h SGMII TX sync FIFO half full threshold
2-0rx_half_full_thR/W3h SGMII RX sync FIFO half full threshold

7.6.2.76 SGMII_FIFO_STATUS Register (Offset = 60Dh) [Reset = 0000h]

SGMII_FIFO_STATUS is shown in Figure 7-95 and described in Table 7-99.

Return to the Summary Table.

Figure 7-95 SGMII_FIFO_STATUS Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDsgmii_rx_af_full_errsgmii_rx_af_empty_errsgmii_tx_af_full_errsgmii_tx_af_empty_err
R-0hR/W0C-0hR/W0C-0hR/W0C-0hR/W0C-0h
Table 7-99 SGMII_FIFO_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR0h Reserved
3sgmii_rx_af_full_errR/W0C0h SGMII RX fifo full error
0h = No error indication
1h = SGMII RX fifo full error has been indicated
2sgmii_rx_af_empty_errR/W0C0h SGMII RX fifo empty error
0h = No error indication
1h = SGMII RX fifo empty error has been indicated
1sgmii_tx_af_full_errR/W0C0h SGMII TX fifo full error
0h = No error indication
1h = SGMII TX fifo full error has been indicated
0sgmii_tx_af_empty_errR/W0C0h SGMII TX fifo empty error
0h = No error indication
1h = SGMII TX fifo empty error has been indicated

7.6.2.77 PRBS_STATUS_1 Register (Offset = 618h) [Reset = 0000h]

PRBS_STATUS_1 is shown in Figure 7-96 and described in Table 7-100.

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Figure 7-96 PRBS_STATUS_1 Register
15141312111098
RESERVED
R-0h
76543210
prbs_err_ov_cnt
R-0h
Table 7-100 PRBS_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0h Reserved
7-0prbs_err_ov_cntR0h Holds number of error counter overflow that received by the PRBS checker. Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. Counter stops on 0xFF. Note: when PRBS counters work in single mode, overflow counter is not active

7.6.2.78 PRBS_CTRL_1 Register (Offset = 619h) [Reset = 0574h]

PRBS_CTRL_1 is shown in Figure 7-97 and described in Table 7-101.

Return to the Summary Table.

Figure 7-97 PRBS_CTRL_1 Register
15141312111098
RESERVEDcfg_pkt_gen_64send_pktRESERVEDcfg_prbs_chk_sel
R-0hR/W-0hR/WMC,0-0hR-0hR/W-5h
76543210
RESERVEDcfg_prbs_gen_selcfg_prbs_cnt_modecfg_prbs_chk_enablecfg_pkt_gen_prbspkt_gen_en
R-0hR/W-7hR/W-0hR/W-1hR/W-0hR/W-0h
Table 7-101 PRBS_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0h Reserved
13cfg_pkt_gen_64R/W0h Reserved
12send_pktR/WMC,00h Enables generating MAC packet with fix/incremental data w CRC (pkt_gen_en has to be set and cfg_pkt_gen_prbs has to be clear) Cleared automatically when pkt_done is set
0h = Stop MAC packet
1h = Transmit MAC packet w CRC
11RESERVEDR0h Reserved
10-8cfg_prbs_chk_selR/W5h 000 : Checker receives from RGMII TX 001 : Checker receives SGMII TX 101 : Checker receives from Cu RX
7RESERVEDR0h Reserved
6-4cfg_prbs_gen_selR/W7h 000 : PRBS transmits to RGMII RX 001 : PRBS transmits to SGMII RX 101 : PRBS transmits to Cu TX
3cfg_prbs_cnt_modeR/W0h 1 = Continuous mode, when one of the PRBS counters reaches max value, pulse is generated and counter starts counting from zero again 0 = Single mode, When one of the PRBS counters reaches max value, PRBS checker stops counting.
2cfg_prbs_chk_enableR/W1h Enable PRBS checker xbar (to receive data) To be enabled for counters in 0x63C, 0x63D, 0x63E to work
0h = Disable PRBS checker
1h = Enable PRBS checker
1cfg_pkt_gen_prbsR/W0h If set: (1) When pkt_gen_en is set, PRBS packets are generated continuously (3) When pkt_gen_en is cleared, PRBS RX checker is still enabled If cleared: (1) When pkt_gen_en is set, non - PRBS packet is generated (3) When pkt_gen_en is cleared, PRBS RX checker is disabled as well
0h = Stop PRBS packet
1h = Transmit PRBS packet
0pkt_gen_enR/W0h 1 = Enable packet/PRBS generator 0 = Disable packet/PRBS generator

7.6.2.79 PRBS_CTRL_2 Register (Offset = 61Ah) [Reset = 05DCh]

PRBS_CTRL_2 is shown in Figure 7-98 and described in Table 7-102.

Return to the Summary Table.

Figure 7-98 PRBS_CTRL_2 Register
15141312111098
cfg_pkt_len_prbs
R/W-5DCh
76543210
cfg_pkt_len_prbs
R/W-5DCh
Table 7-102 PRBS_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0cfg_pkt_len_prbsR/W5DCh Length (in bytes) of PRBS packets and MAC packets w CRC

7.6.2.80 PRBS_CTRL_3 Register (Offset = 61Bh) [Reset = 007Dh]

PRBS_CTRL_3 is shown in Figure 7-99 and described in Table 7-103.

Return to the Summary Table.

Figure 7-99 PRBS_CTRL_3 Register
15141312111098
RESERVED
R-0h
76543210
cfg_ipg_len
R/W-7Dh
Table 7-103 PRBS_CTRL_3 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0h Reserved
7-0cfg_ipg_lenR/W7Dh Inter-packet gap (in bytes) between packets

7.6.2.81 PRBS_STATUS_2 Register (Offset = 61Ch) [Reset = 0000h]

PRBS_STATUS_2 is shown in Figure 7-100 and described in Table 7-104.

Return to the Summary Table.

Figure 7-100 PRBS_STATUS_2 Register
15141312111098
prbs_byte_cnt
R-0h
76543210
prbs_byte_cnt
R-0h
Table 7-104 PRBS_STATUS_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0prbs_byte_cntR0h Holds number of total bytes that received by the PRBS checker. Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFF

7.6.2.82 PRBS_STATUS_3 Register (Offset = 61Dh) [Reset = 0000h]

PRBS_STATUS_3 is shown in Figure 7-101 and described in Table 7-105.

Return to the Summary Table.

Figure 7-101 PRBS_STATUS_3 Register
15141312111098
prbs_pkt_cnt_15_0
R-0h
76543210
prbs_pkt_cnt_15_0
R-0h
Table 7-105 PRBS_STATUS_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0prbs_pkt_cnt_15_0R0h Bits [15:0] of number of total packets received by the PRBS checker Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF

7.6.2.83 PRBS_STATUS_4 Register (Offset = 61Eh) [Reset = 0000h]

PRBS_STATUS_4 is shown in Figure 7-102 and described in Table 7-106.

Return to the Summary Table.

Figure 7-102 PRBS_STATUS_4 Register
15141312111098
prbs_pkt_cnt_31_16
R-0h
76543210
prbs_pkt_cnt_31_16
R-0h
Table 7-106 PRBS_STATUS_4 Register Field Descriptions
BitFieldTypeResetDescription
15-0prbs_pkt_cnt_31_16R0h Bits [31:16] of number of total packets received by the PRBS checker Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF

7.6.2.84 PRBS_STATUS_6 Register (Offset = 620h) [Reset = 0000h]

PRBS_STATUS_6 is shown in Figure 7-103 and described in Table 7-107.

Return to the Summary Table.

Figure 7-103 PRBS_STATUS_6 Register
15141312111098
RESERVEDpkt_donepkt_gen_busyprbs_pkt_ovprbs_byte_ovprbs_lock
R-0hR-0hR-0hR-0hR-0hR-0h
76543210
prbs_err_cnt
R-0h
Table 7-107 PRBS_STATUS_6 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h Reserved
12pkt_doneR0h Set when all MAC packets w CRC are transmitted
0h = MAC packet transmission in progress
1h = MAC packets transmission completed
11pkt_gen_busyR0h 1 = Packet generator is in process 0 = Packet generator is not in process
10prbs_pkt_ovR0h If set, packet counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit #1 of prbs_status_6
0h = No overflow
1h = Packet counter overflow
9prbs_byte_ovR0h If set, bytes counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit #1of prbs_status_6
0h = No overflow
1h = byte counter overflow
8prbs_lockR0h 1 = PRBS checker is locked sync) on received byte stream 0 = PRBS checker is not locked
0h = PRBS checker is not locked
1h = PRBS checker is locked sync) on received byte stream
7-0prbs_err_cntR0h Holds number of errored bits received by the PRBS checker Value in this register is locked when write is done to bit[0] or bit[1] When PRBS Count Mode set to zero, count stops on 0xFF Notes: Writing bit 0 generates a lock signal for the PRBS counters. Writing bit 1 generates a lock and clear signal for the PRBS counters

7.6.2.85 PRBS_STATUS_8 Register (Offset = 622h) [Reset = 0000h]

PRBS_STATUS_8 is shown in Figure 7-104 and described in Table 7-108.

Return to the Summary Table.

Figure 7-104 PRBS_STATUS_8 Register
15141312111098
pkt_err_cnt_15_0
R-0h
76543210
pkt_err_cnt_15_0
R-0h
Table 7-108 PRBS_STATUS_8 Register Field Descriptions
BitFieldTypeResetDescription
15-0pkt_err_cnt_15_0R0h Bits [15:0] of number of total packets with error received by the PRBS checker Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF

7.6.2.86 PRBS_STATUS_9 Register (Offset = 623h) [Reset = 0000h]

PRBS_STATUS_9 is shown in Figure 7-105 and described in Table 7-109.

Return to the Summary Table.

Figure 7-105 PRBS_STATUS_9 Register
15141312111098
pkt_err_cnt_31_16
R-0h
76543210
pkt_err_cnt_31_16
R-0h
Table 7-109 PRBS_STATUS_9 Register Field Descriptions
BitFieldTypeResetDescription
15-0pkt_err_cnt_31_16R0h Bits [31:16] of number of total packets with error received by the PRBS checker Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF

7.6.2.87 PRBS_CTRL_4 Register (Offset = 624h) [Reset = 5511h]

PRBS_CTRL_4 is shown in Figure 7-106 and described in Table 7-110.

Return to the Summary Table.

Figure 7-106 PRBS_CTRL_4 Register
15141312111098
cfg_pkt_data
R/W-55h
76543210
cfg_pkt_modecfg_pattern_vld_bytescfg_pkt_cnt
R/W-0hR/W-2hR/W-1h
Table 7-110 PRBS_CTRL_4 Register Field Descriptions
BitFieldTypeResetDescription
15-8cfg_pkt_dataR/W55h Fixed data to be sent in Fix data mode
7-6cfg_pkt_modeR/W0h 2b00 - Incremental 2b01 - Fixed 2b1x - PRBS
0h = Incremental
1h = Fixed
5-3cfg_pattern_vld_bytesR/W2h Number of bytes of valid pattern in packet (Max - 6)
0h = 0 bytes
1h = 1 bytes
2h = 2 bytes
3h = 3 bytes
4h = 4 bytes
5h = 5 bytes
6h = 6 bytes
7h = 6 bytes
2-0cfg_pkt_cntR/W1h 000b = 1 packet 001b = 10 packets 010b = 100 packets 011b = 1000 packets 100b = 10000 packets 101b = 100000 packets 110b = 1000000 packets 111b = Continuous packets
0h = 1 packet
1h = 10 packets
2h = 100 packets
3h = 1000 packets
4h = 10000 packets
5h = 100000 packets
6h = 1000000 packets
7h = Continuous packets

7.6.2.88 PRBS_CTRL_5 Register (Offset = 625h) [Reset = 0000h]

PRBS_CTRL_5 is shown in Figure 7-107 and described in Table 7-111.

Return to the Summary Table.

Figure 7-107 PRBS_CTRL_5 Register
15141312111098
pattern_15_0
R/W-0h
76543210
pattern_15_0
R/W-0h
Table 7-111 PRBS_CTRL_5 Register Field Descriptions
BitFieldTypeResetDescription
15-0pattern_15_0R/W0h Bits 15:0 of pattern

7.6.2.89 PRBS_CTRL_6 Register (Offset = 626h) [Reset = 0000h]

PRBS_CTRL_6 is shown in Figure 7-108 and described in Table 7-112.

Return to the Summary Table.

Figure 7-108 PRBS_CTRL_6 Register
15141312111098
pattern_31_16
R/W-0h
76543210
pattern_31_16
R/W-0h
Table 7-112 PRBS_CTRL_6 Register Field Descriptions
BitFieldTypeResetDescription
15-0pattern_31_16R/W0h Bits 31:16 of pattern

7.6.2.90 PRBS_CTRL_7 Register (Offset = 627h) [Reset = 0000h]

PRBS_CTRL_7 is shown in Figure 7-109 and described in Table 7-113.

Return to the Summary Table.

Figure 7-109 PRBS_CTRL_7 Register
15141312111098
pattern_47_32
R/W-0h
76543210
pattern_47_32
R/W-0h
Table 7-113 PRBS_CTRL_7 Register Field Descriptions
BitFieldTypeResetDescription
15-0pattern_47_32R/W0h Bits 47:32 of pattern

7.6.2.91 PRBS_CTRL_8 Register (Offset = 628h) [Reset = 0000h]

PRBS_CTRL_8 is shown in Figure 7-110 and described in Table 7-114.

Return to the Summary Table.

Figure 7-110 PRBS_CTRL_8 Register
15141312111098
pmatch_data_15_0
R/W-0h
76543210
pmatch_data_15_0
R/W-0h
Table 7-114 PRBS_CTRL_8 Register Field Descriptions
BitFieldTypeResetDescription
15-0pmatch_data_15_0R/W0h Bits 15:0 of Perfect Match Data - used for DA (destination address) match

7.6.2.92 PRBS_CTRL_9 Register (Offset = 629h) [Reset = 0000h]

PRBS_CTRL_9 is shown in Figure 7-111 and described in Table 7-115.

Return to the Summary Table.

Figure 7-111 PRBS_CTRL_9 Register
15141312111098
pmatch_data_31_16
R/W-0h
76543210
pmatch_data_31_16
R/W-0h
Table 7-115 PRBS_CTRL_9 Register Field Descriptions
BitFieldTypeResetDescription
15-0pmatch_data_31_16R/W0h Bits 31:16 of Perfect Match Data - used for DA (destination address) match

7.6.2.93 PRBS_CTRL_10 Register (Offset = 62Ah) [Reset = 0000h]

PRBS_CTRL_10 is shown in Figure 7-112 and described in Table 7-116.

Return to the Summary Table.

Figure 7-112 PRBS_CTRL_10 Register
15141312111098
pmatch_data_47_32
R/W-0h
76543210
pmatch_data_47_32
R/W-0h
Table 7-116 PRBS_CTRL_10 Register Field Descriptions
BitFieldTypeResetDescription
15-0pmatch_data_47_32R/W0h Bits 47:32 of Perfect Match Data - used for DA (destination address) match

7.6.2.94 CRC_STATUS Register (Offset = 638h) [Reset = 0000h]

CRC_STATUS is shown in Figure 7-113 and described in Table 7-117.

Return to the Summary Table.

Figure 7-113 CRC_STATUS Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDrx_bad_crctx_bad_crc
R-0hR-0hR-0h
Table 7-117 CRC_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0h Reserved
1rx_bad_crcR0h CRC error indication in packet received on Cu RX
0h = No CRC error
1h = CRC error
0tx_bad_crcR0h CRC error indication in packet transmitted on Cu TX
0h = No CRC error
1h = CRC error

7.6.2.95 PKT_STAT_1 Register (Offset = 639h) [Reset = 0000h]

PKT_STAT_1 is shown in Figure 7-114 and described in Table 7-118.

Return to the Summary Table.

Figure 7-114 PKT_STAT_1 Register
15141312111098
tx_pkt_cnt_15_0
0h
76543210
tx_pkt_cnt_15_0
0h
Table 7-118 PKT_STAT_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0tx_pkt_cnt_15_00h Lower 16 bits of Tx packet counter Note : Register is cleared when 0x39, 0x3A, 0x3B are read in sequence

7.6.2.96 PKT_STAT_2 Register (Offset = 63Ah) [Reset = 0000h]

PKT_STAT_2 is shown in Figure 7-115 and described in Table 7-119.

Return to the Summary Table.

Figure 7-115 PKT_STAT_2 Register
15141312111098
tx_pkt_cnt_31_16
0h
76543210
tx_pkt_cnt_31_16
0h
Table 7-119 PKT_STAT_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0tx_pkt_cnt_31_160h Upper 16 bits of Tx packet counter Note : Register is cleared when 0x39, 0x3A, 0x3B are read in sequence

7.6.2.97 PKT_STAT_3 Register (Offset = 63Bh) [Reset = 0000h]

PKT_STAT_3 is shown in Figure 7-116 and described in Table 7-120.

Return to the Summary Table.

Figure 7-116 PKT_STAT_3 Register
15141312111098
tx_err_pkt_cnt
0h
76543210
tx_err_pkt_cnt
0h
Table 7-120 PKT_STAT_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0tx_err_pkt_cnt0h Tx packet w error (CRC error) counter Note : Register is cleared when 0x39, 0x3A, 0x3B are read in sequence

7.6.2.98 PKT_STAT_4 Register (Offset = 63Ch) [Reset = 0000h]

PKT_STAT_4 is shown in Figure 7-117 and described in Table 7-121.

Return to the Summary Table.

Figure 7-117 PKT_STAT_4 Register
15141312111098
rx_pkt_cnt_15_0
0h
76543210
rx_pkt_cnt_15_0
0h
Table 7-121 PKT_STAT_4 Register Field Descriptions
BitFieldTypeResetDescription
15-0rx_pkt_cnt_15_00h Lower 16 bits of Rx packet counter Note : Register is cleared when 0x3C, 0x3D, 0x3E are read in sequence

7.6.2.99 PKT_STAT_5 Register (Offset = 63Dh) [Reset = 0000h]

PKT_STAT_5 is shown in Figure 7-118 and described in Table 7-122.

Return to the Summary Table.

Figure 7-118 PKT_STAT_5 Register
15141312111098
rx_pkt_cnt_31_16
0h
76543210
rx_pkt_cnt_31_16
0h
Table 7-122 PKT_STAT_5 Register Field Descriptions
BitFieldTypeResetDescription
15-0rx_pkt_cnt_31_160h Upper 16 bits of Rx packet counter Note : Register is cleared when 0x3C, 0x3D, 0x3E are read in sequence

7.6.2.100 PKT_STAT_6 Register (Offset = 63Eh) [Reset = 0000h]

PKT_STAT_6 is shown in Figure 7-119 and described in Table 7-123.

Return to the Summary Table.

Figure 7-119 PKT_STAT_6 Register
15141312111098
rx_err_pkt_cnt
0h
76543210
rx_err_pkt_cnt
0h
Table 7-123 PKT_STAT_6 Register Field Descriptions
BitFieldTypeResetDescription
15-0rx_err_pkt_cnt0h Rx packet w error (CRC error) counter Note : Register is cleared when 0x3C, 0x3D, 0x3E are read in sequence

7.6.2.101 SQI_REG_1 Register (Offset = 871h) [Reset = 0000h]

SQI_REG_1 is shown in Figure 7-120 and described in Table 7-124.

Return to the Summary Table.

Figure 7-120 SQI_REG_1 Register
15141312111098
RESERVED
R-0h
76543210
worst_sqi_outRESERVEDsqi_outRESERVED
0hR-0hR-0hR-0h
Table 7-124 SQI_REG_1 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0h Reserved
7-5worst_sqi_out0h 3 bit Worst SQI since last read (see SQI mapping above)
4RESERVEDR0h Reserved
3-1sqi_outR0h 3 bit SQI - (mse here refers to Mean Square Error 0x875[9:0]) 0b000 = MSE > 102 0b001 = 81 < MSE ≤102 0b010 = 65 < MSE ≤ 81 0b011 = 51 < MSE ≤ 65 0b100 = 41 < MSE ≤ 51 0b101 = 32 < MSE ≤ 41 0b110 = 25 < MSE ≤ 32 0b111 = MSE ≤ 25
0RESERVEDR0h Reserved

7.6.2.102 DSP_REG_75 Register (Offset = 875h) [Reset = 0000h]

DSP_REG_75 is shown in Figure 7-121 and described in Table 7-125.

Return to the Summary Table.

Figure 7-121 DSP_REG_75 Register
15141312111098
RESERVEDRESERVEDmse_lock
R-0hR-0hR-0h
76543210
mse_lock
R-0h
Table 7-125 DSP_REG_75 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0h Reserved
11-10RESERVEDR0h Reserved
9-0mse_lockR0h 10 bit mse used for SQI mapping. (mse = mean square error at the receiver)

7.6.2.103 SQI_1 Register (Offset = 8ADh) [Reset = 3051h]

SQI_1 is shown in Figure 7-122 and described in Table 7-126.

Return to the Summary Table.

Figure 7-122 SQI_1 Register
15141312111098
cfg_hist_1_2cfg_acc_window_selcfg_sqi_th_1_2
R/W-3hR/W-0hR/W-51h
76543210
cfg_sqi_th_1_2
R/W-51h
Table 7-126 SQI_1 Register Field Descriptions
BitFieldTypeResetDescription
15-12cfg_hist_1_2R/W3h Hysteresis between SQI value 1 and 2
11-10cfg_acc_window_selR/W0h Accumulator window select - 00b = 90us 01b = 180us 10b = 360us 11b = 720us
9-0cfg_sqi_th_1_2R/W51h Threshold between SQI value 1 and 2

7.6.2.104 PMA_PMD_CONTROL_1 Register (Offset = 1000h) [Reset = 0000h]

PMA_PMD_CONTROL_1 is shown in Figure 7-123 and described in Table 7-127.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-123 PMA_PMD_CONTROL_1 Register
15141312111098
pma_reset_2RESERVEDcfg_low_power_2RESERVED
R-0hR-0hR-0hR-0h
76543210
RESERVED
R-0h
Table 7-127 PMA_PMD_CONTROL_1 Register Field Descriptions
BitFieldTypeResetDescription
15pma_reset_2R0h 1 = PMA/PMD reset 0 = Normal operation Note - RW bit, self clearing
14-12RESERVEDR0h Reserved
11cfg_low_power_2R0h 1 = Low-power mode 0 = Normal operation Note - RW bit
10-0RESERVEDR0h Reserved

7.6.2.105 PMA_PMD_CONTROL_2 Register (Offset = 1007h) [Reset = 003Dh]

PMA_PMD_CONTROL_2 is shown in Figure 7-124 and described in Table 7-128.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-124 PMA_PMD_CONTROL_2 Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDcfg_pma_type_selection
R-0hR/W-3Dh
Table 7-128 PMA_PMD_CONTROL_2 Register Field Descriptions
BitFieldTypeResetDescription
15-6RESERVEDR0h Reserved
5-0cfg_pma_type_selectionR/W3Dh BASE-T1 type selection for device
3Dh = BASE-T1 type selection for device

7.6.2.106 PMA_PMD_TRANSMIT_DISABLE Register (Offset = 1009h) [Reset = 0000h]

PMA_PMD_TRANSMIT_DISABLE is shown in Figure 7-125 and described in Table 7-129.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-125 PMA_PMD_TRANSMIT_DISABLE Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDcfg_transmit_disable_2
R-0hR-0h
Table 7-129 PMA_PMD_TRANSMIT_DISABLE Register Field Descriptions
BitFieldTypeResetDescription
15-1RESERVEDR0h Reserved
0cfg_transmit_disable_2R0h 1 = Transmit disable 0 = Normal operation Note - RW bit

7.6.2.107 PMA_PMD_EXTENDED_ABILITY2 Register (Offset = 100Bh) [Reset = 0800h]

PMA_PMD_EXTENDED_ABILITY2 is shown in Figure 7-126 and described in Table 7-130.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-126 PMA_PMD_EXTENDED_ABILITY2 Register
15141312111098
RESERVEDbase_t1_extended_abilitiesRESERVED
R-0hR-1hR-0h
76543210
RESERVED
R-0h
Table 7-130 PMA_PMD_EXTENDED_ABILITY2 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0h Reserved
11base_t1_extended_abilitiesR1h 1 = PMA/PMD has BASE-T1 extended abilities listed in register 1.18 0 = PMA/PMD does not have BASE-T1 extended abilities
10-0RESERVEDR0h Reserved

7.6.2.108 PMA_PMD_EXTENDED_ABILITY Register (Offset = 1012h) [Reset = 0002h]

PMA_PMD_EXTENDED_ABILITY is shown in Figure 7-127 and described in Table 7-131.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-127 PMA_PMD_EXTENDED_ABILITY Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDmr_1000_base_t1_abilitymr_100_base_t1_ability
R-0hR-1hR-0h
Table 7-131 PMA_PMD_EXTENDED_ABILITY Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0h Reserved
1mr_1000_base_t1_abilityR1h 1 = PMA/PMD is able to perform 1000BASE-T1 0 = PMA/PMD is not able to perform 1000BASE-T1
0mr_100_base_t1_abilityR0h 1 = PMA/PMD is able to perform 100BASE-T1 0 = PMA/PMD is not able to perform 100BASE-T1

7.6.2.109 PMA_PMD_CONTROL Register (Offset = 1834h) [Reset = 8001h]

PMA_PMD_CONTROL is shown in Figure 7-128 and described in Table 7-132.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-128 PMA_PMD_CONTROL Register
15141312111098
RESERVEDcfg_master_slave_valRESERVED
R-1hR/W-0hR-0h
76543210
RESERVEDRESERVED
R-0hR/W-1h
Table 7-132 PMA_PMD_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR1h Reserved
14cfg_master_slave_valR/W0h 1 = Configure PHY as MASTER 0 = Configure PHY as SLAVE
13-4RESERVEDR0h Reserved
3-0RESERVEDR/W1h Reserved

7.6.2.110 PMA_CONTROL Register (Offset = 1900h) [Reset = 0000h]

PMA_CONTROL is shown in Figure 7-129 and described in Table 7-133.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-129 PMA_CONTROL Register
15141312111098
pma_resetcfg_transmit_disableRESERVEDcfg_low_powerRESERVED
R-0hR-0hR-0hR-0hR-0h
76543210
RESERVED
R-0h
Table 7-133 PMA_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
15pma_resetR0h 1 = PMA/PMD reset 0 = Normal operation Note - RW bit, self clearing
14cfg_transmit_disableR0h 1 = Transmit disable 0 = Normal operation Note - RW bit
13-12RESERVEDR0h Reserved
11cfg_low_powerR0h 1 = Low-power mode 0 = Normal operation Note - RW bit
10-0RESERVEDR0h Reserved

7.6.2.111 PMA_STATUS Register (Offset = 1901h) [Reset = 0900h]

PMA_STATUS is shown in Figure 7-130 and described in Table 7-134.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-130 PMA_STATUS Register
15141312111098
RESERVEDoam_abilityeee_abilityreceive_fault_abilitylow_power_ability
R-0hR-1hR-0hR-0hR-1h
76543210
RESERVEDreceive_polarityreceive_faultpma_receive_link_status_ll
R-0hR-0hR-0hR/W0S-0h
Table 7-134 PMA_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0h Reserved
11oam_abilityR1h 1 = PHY has 1000BASE-T1 OAM ability 0 = PHY does not have 1000BASE-T1 OAM ability
10eee_abilityR0h 1 = PHY has EEE ability 0 = PHY does not have EEE ability
9receive_fault_abilityR0h 1 = PMA/PMD has the ability to detect a fault condition on the receive path 0 = PMA/PMD does not have the ability to detect a fault condition on the receive path
8low_power_abilityR1h 1 = PMA/PMD has low-power ability 0 = PMA/PMD does not have low-power ability
7-3RESERVEDR0h Reserved
2receive_polarityR0h 1 = Receive polarity is reversed 0 = Receive polarity is not reversed
1receive_faultR0h 1 = Fault condition detected 0 = Fault condition not detected

7.6.2.112 TRAINING Register (Offset = 1902h) [Reset = 0002h]

TRAINING is shown in Figure 7-131 and described in Table 7-135.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-131 TRAINING Register
15141312111098
RESERVEDcfg_training_user_fld
R-0hR/W-0h
76543210
cfg_training_user_fldRESERVEDcfg_oam_encfg_eee_en
R/W-0hR-0hR/W-1hR/W-0h
Table 7-135 TRAINING Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10-4cfg_training_user_fldR/W0h 7-bit user defined field to send to the link partner
3-2RESERVEDR0h Reserved
1cfg_oam_enR/W1h 1 = 1000BASE-T1 OAM ability advertised to link partner 0 = 1000BASE-T1 OAM ability not advertised to link partner
0cfg_eee_enR/W0h 1 = EEE ability advertised to link partner 0 = EEE ability not advertised to link partner

7.6.2.113 LP_TRAINING Register (Offset = 1903h) [Reset = 0000h]

LP_TRAINING is shown in Figure 7-132 and described in Table 7-136.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-132 LP_TRAINING Register
15141312111098
RESERVEDlp_training_user_fld
R-0hR-0h
76543210
lp_training_user_fldRESERVEDlp_oam_advlp_eee_adv
R-0hR-0hR-0hR-0h
Table 7-136 LP_TRAINING Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10-4lp_training_user_fldR0h 7-bit user defined field received from the link partner
3-2RESERVEDR0h Reserved
1lp_oam_advR0h 1 = Link partner has 1000BASE-T1 OAM ability 0 = Link partner does not have 1000BASE-T1 OAM ability
0lp_eee_advR0h 1 = Link partner has EEE ability 0 = Link partner does not have EEE ability

7.6.2.114 TEST_MODE_CONTROL Register (Offset = 1904h) [Reset = 0000h]

TEST_MODE_CONTROL is shown in Figure 7-133 and described in Table 7-137.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-133 TEST_MODE_CONTROL Register
15141312111098
cfg_test_modeRESERVED
R/W-0hR-0h
76543210
RESERVED
R-0h
Table 7-137 TEST_MODE_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
15-13cfg_test_modeR/W0h 111 = Test mode 7 110 = Test mode 6 101 = Test mode 5 100 = Test mode 4 011 = Reserved 010 = Test mode 2 001 = Test mode 1 000 = Normal (non-test) operation
12-0RESERVEDR0h Reserved

7.6.2.115 PCS_CONTROL_COPY Register (Offset = 3000h) [Reset = 0000h]

PCS_CONTROL_COPY is shown in Figure 7-134 and described in Table 7-138.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-134 PCS_CONTROL_COPY Register
15141312111098
pcs_reset_2mmd3_loopback_2RESERVED
R-0hR-0hR-0h
76543210
RESERVED
R-0h
Table 7-138 PCS_CONTROL_COPY Register Field Descriptions
BitFieldTypeResetDescription
15pcs_reset_2R0h Note - RW bit, self clear bit
0h = Normal operation
1h = PCS reset
14mmd3_loopback_2R0h Note - RW bit
0h = Disable loopback mode
1h = Enable loopback mode
13-0RESERVEDR0h Reserved

7.6.2.116 PCS_CONTROL Register (Offset = 3900h) [Reset = 0000h]

PCS_CONTROL is shown in Figure 7-135 and described in Table 7-139.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-135 PCS_CONTROL Register
15141312111098
pcs_resetmmd3_loopbackRESERVED
R-0hR-0hR-0h
76543210
RESERVED
R-0h
Table 7-139 PCS_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
15pcs_resetR0h Note - RW bit, self clear bit
0h = Normal operation
1h = PCS reset
14mmd3_loopbackR0h Note - RW bit
0h = Disable loopback mode
1h = Enable loopback mode
13-0RESERVEDR0h Reserved

7.6.2.117 PCS_STATUS Register (Offset = 3901h) [Reset = 0000h]

PCS_STATUS is shown in Figure 7-136 and described in Table 7-140.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-136 PCS_STATUS Register
15141312111098
RESERVEDtx_lpi_received_lhrx_lpi_received_lhtx_lpi_indicationrx_lpi_indication
R-0hR/W0C-0hR/W0C-0hR-0hR-0h
76543210
pcs_faultRESERVEDpcs_receive_link_status_llRESERVED
R-0hR-0hR/W0S-0hR-0h
Table 7-140 PCS_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0h Reserved
11tx_lpi_received_lhR/W0C0h
0h = LPI not received
1h = Tx PCS has received LPI
10rx_lpi_received_lhR/W0C0h
0h = LPI not received
1h = Rx PCS has received LPI
9tx_lpi_indicationR0h
0h = PCS is not currently receiving LPI
1h = Tx PCS is currently receiving LPI
8rx_lpi_indicationR0h
0h = PCS is not currently receiving LPI
1h = Rx PCS is currently receiving LPI
7pcs_faultR0h
0h = No fault condition detected
1h = Fault condition detected
6-3RESERVEDR0h Reserved
1-0RESERVEDR0h Reserved

7.6.2.118 PCS_STATUS_2 Register (Offset = 3902h) [Reset = 0000h]

PCS_STATUS_2 is shown in Figure 7-137 and described in Table 7-141.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-137 PCS_STATUS_2 Register
15141312111098
RESERVEDpcs_receive_link_statushi_rferblock_lock
R-0hR-0hR-0hR-0h
76543210
hi_rfer_lhblock_lock_llRESERVED
R/W0C-0hR/W0S-0hR-0h
Table 7-141 PCS_STATUS_2 Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
9hi_rferR0h
0h = PCS not reporting a high BER
1h = PCS reporting a high BER
8block_lockR0h
0h = PCS not locked to received blocks
1h = PCS locked to received blocks
7hi_rfer_lhR/W0C0h
0h = PCS has not reported a high BER
1h = PCS has reported a high BER
6block_lock_llR/W0S0h
0h = PCS does not have block lock
1h = PCS has block lock
5-0RESERVEDR0h Reserved

7.6.2.119 OAM_TRANSMIT Register (Offset = 3904h) [Reset = 0000h]

OAM_TRANSMIT is shown in Figure 7-138 and described in Table 7-142.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-138 OAM_TRANSMIT Register
15141312111098
mr_tx_validmr_tx_togglemr_tx_receivedmr_tx_received_togglemr_tx_message_num
R/WMC,0-0hR-0h0hR-0hR/W-0h
76543210
RESERVEDmr_rx_pingmr_tx_pingmr_tx_snr
R-0hR-0hR/W-0hR-0h
Table 7-142 OAM_TRANSMIT Register Field Descriptions
BitFieldTypeResetDescription
15mr_tx_validR/WMC,00h This bit is used to indicate message data in registers 3.2308.11:8, 3.2309, 3.2310, 3.2311, and 3.2312 are valid and ready to be loaded. This bit shall self-clear when registers are loaded by the state machine. 1 = Message data in registers are valid 0 = Message data in registers are not valid
14mr_tx_toggleR0h Toggle value to be transmitted with message. This bit is set by the state machine and cannot be overridden by the user.
13mr_tx_received0h This bit shall self clear on read. 1 = 1000BASE-T1 OAM message received by link partner 0 = 1000BASE-T1 OAM message not received by link partner
12mr_tx_received_toggleR0h Toggle value of message that was received by link partner
11-8mr_tx_message_numR/W0h User-defined message number to send
7-4RESERVEDR0h Reserved
3mr_rx_pingR0h Received PingTx value from latest good 1000BASE-T1 OAM frame received
2mr_tx_pingR/W0h Ping value to send to link partner
1-0mr_tx_snrR0h 00 = PHY link is failing and will drop link and relink within 2 ms to 4 ms after the end of the current 1000BASE-T1 OAM frame. 01 = LPI refresh is insufficient to maintain PHY SNR. Request link partner to exit LPI and send idles (used only when EEE is enabled). 10 = PHY SNR is marginal. 11 = PHY SNR is good.

7.6.2.120 OAM_TX_MESSAGE_1 Register (Offset = 3905h) [Reset = 0000h]

OAM_TX_MESSAGE_1 is shown in Figure 7-139 and described in Table 7-143.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-139 OAM_TX_MESSAGE_1 Register
15141312111098
mr_tx_message_15_0
R/W-0h
76543210
mr_tx_message_15_0
R/W-0h
Table 7-143 OAM_TX_MESSAGE_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0mr_tx_message_15_0R/W0h Message octet 1/0. LSB transmitted first.

7.6.2.121 OAM_TX_MESSAGE_2 Register (Offset = 3906h) [Reset = 0000h]

OAM_TX_MESSAGE_2 is shown in Figure 7-140 and described in Table 7-144.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-140 OAM_TX_MESSAGE_2 Register
15141312111098
mr_tx_message_31_16
R/W-0h
76543210
mr_tx_message_31_16
R/W-0h
Table 7-144 OAM_TX_MESSAGE_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0mr_tx_message_31_16R/W0h Message octet 3/2. LSB transmitted first.

7.6.2.122 OAM_TX_MESSAGE_3 Register (Offset = 3907h) [Reset = 0000h]

OAM_TX_MESSAGE_3 is shown in Figure 7-141 and described in Table 7-145.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-141 OAM_TX_MESSAGE_3 Register
15141312111098
mr_tx_message_47_32
R/W-0h
76543210
mr_tx_message_47_32
R/W-0h
Table 7-145 OAM_TX_MESSAGE_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0mr_tx_message_47_32R/W0h Message octet 5/4. LSB transmitted first.

7.6.2.123 OAM_TX_MESSAGE_4 Register (Offset = 3908h) [Reset = 0000h]

OAM_TX_MESSAGE_4 is shown in Figure 7-142 and described in Table 7-146.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-142 OAM_TX_MESSAGE_4 Register
15141312111098
mr_tx_message_63_48
R/W-0h
76543210
mr_tx_message_63_48
R/W-0h
Table 7-146 OAM_TX_MESSAGE_4 Register Field Descriptions
BitFieldTypeResetDescription
15-0mr_tx_message_63_48R/W0h Message octet 7/6. LSB transmitted first.

7.6.2.124 OAM_RECEIVE Register (Offset = 3909h) [Reset = 0000h]

OAM_RECEIVE is shown in Figure 7-143 and described in Table 7-147.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-143 OAM_RECEIVE Register
15141312111098
mr_rx_lp_validmr_rx_lp_toggleRESERVEDmr_rx_lp_message_num
R-0hR-0hR-0hR-0h
76543210
RESERVEDmr_rx_lp_SNR
R-0hR-0h
Table 7-147 OAM_RECEIVE Register Field Descriptions
BitFieldTypeResetDescription
15mr_rx_lp_validR0h This bit is used to indicate message data in registers 3.2313.11:8, 3.2314, 3.2315, 3.2316, and 3.2317 are stored and ready to be read. This bit shall self clear when register 3.2317 is read.
0h = Message data in registers are not valid
1h = Message data in registers are valid
14mr_rx_lp_toggleR0h Toggle value received with message Note - 0x3 added in [15:12] to differentiate
13-12RESERVEDR0h Reserved
11-8mr_rx_lp_message_numR0h Message number from link partner Note - 0x3 added in [15:12] to differentiate
7-2RESERVEDR0h Reserved
1-0mr_rx_lp_SNRR0h 00 = Link partner link is failing and will drop link and relink within 2 ms to 4 ms after the end of the current 1000BASE-T1 OAM frame. 01 = LPI refresh is insufficient to maintain link partner SNR. Link partner requests local device to exit LPI and send idles (used only when EEE is enabled). 10 = Link partner SNR is marginal. 11 = Link partner SNR is good

7.6.2.125 OAM_RX_MESSAGE_1 Register (Offset = 390Ah) [Reset = 0000h]

OAM_RX_MESSAGE_1 is shown in Figure 7-144 and described in Table 7-148.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-144 OAM_RX_MESSAGE_1 Register
15141312111098
mr_rx_lp_message_15_0
R-0h
76543210
mr_rx_lp_message_15_0
R-0h
Table 7-148 OAM_RX_MESSAGE_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0mr_rx_lp_message_15_0R0h Message octet 1/0. LSB transmitted first.

7.6.2.126 OAM_RX_MESSAGE_2 Register (Offset = 390Bh) [Reset = 0000h]

OAM_RX_MESSAGE_2 is shown in Figure 7-145 and described in Table 7-149.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-145 OAM_RX_MESSAGE_2 Register
15141312111098
mr_rx_lp_message_31_16
R-0h
76543210
mr_rx_lp_message_31_16
R-0h
Table 7-149 OAM_RX_MESSAGE_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0mr_rx_lp_message_31_16R0h Message octet 3/2. LSB transmitted first.

7.6.2.127 OAM_RX_MESSAGE_3 Register (Offset = 390Ch) [Reset = 0000h]

OAM_RX_MESSAGE_3 is shown in Figure 7-146 and described in Table 7-150.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-146 OAM_RX_MESSAGE_3 Register
15141312111098
mr_rx_lp_message_47_32
R-0h
76543210
mr_rx_lp_message_47_32
R-0h
Table 7-150 OAM_RX_MESSAGE_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0mr_rx_lp_message_47_32R0h Message octet 5/4. LSB transmitted first.

7.6.2.128 OAM_RX_MESSAGE_4 Register (Offset = 390Dh) [Reset = 0000h]

OAM_RX_MESSAGE_4 is shown in Figure 7-147 and described in Table 7-151.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-147 OAM_RX_MESSAGE_4 Register
15141312111098
mr_rx_lp_message_63_48
0h
76543210
mr_rx_lp_message_63_48
0h
Table 7-151 OAM_RX_MESSAGE_4 Register Field Descriptions
BitFieldTypeResetDescription
15-0mr_rx_lp_message_63_480h Message octet 7/6. LSB transmitted first.

7.6.2.129 AN_CFG Register (Offset = 7200h) [Reset = 0000h]

AN_CFG is shown in Figure 7-148 and described in Table 7-152.

Return to the Summary Table.

First nibble (0x7) in the register address is to indicated MMD register space. For register access, ignore the first nibble.

Figure 7-148 AN_CFG Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDmr_main_reset
R-0hR/WSC-0h
Table 7-152 AN_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-1RESERVEDR0h Reserved
0mr_main_resetR/WSC0h 1 = Reset link sync/autoneg Note - RW bit Note - Added 7 to [15:12] to differentiate