SNLS604E September   2020  – November 2022 DP83TG720S-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2. 5.1 Pin States
    3. 5.2 Pin Power Domain
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 LED Drive Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Diagnostic Tool Kit
        1. 7.3.1.1 Signal Quality Indicator
        2. 7.3.1.2 Time Domain Reflectometry
        3. 7.3.1.3 Built-In Self-Test For Datapath
          1. 7.3.1.3.1 Loopback Modes
          2. 7.3.1.3.2 Data Generator
          3. 7.3.1.3.3 Programming Datapath BIST
        4. 7.3.1.4 Temperature and Voltage Sensing
        5. 7.3.1.5 Electrostatic Discharge Sensing
      2. 7.3.2 Compliance Test Modes
        1. 7.3.2.1 Test Mode 1
        2. 7.3.2.2 Test Mode 2
        3. 7.3.2.3 Test Mode 4
        4. 7.3.2.4 Test Mode 5
        5. 7.3.2.5 Test Mode 6
        6. 7.3.2.6 Test Mode 7
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Down
      2. 7.4.2  Reset
      3. 7.4.3  Standby
      4. 7.4.4  Normal
      5. 7.4.5  Sleep
      6. 7.4.6  State Transitions
        1. 7.4.6.1 State Transition #1 - Standby to Normal
        2. 7.4.6.2 State Transition #2 - Normal to Standby
        3. 7.4.6.3 State Transition #3 - Normal to Sleep
        4. 7.4.6.4 State Transition #4 - Sleep to Normal
      7. 7.4.7  Media Dependent Interface
        1. 7.4.7.1 MDI Master and MDI Slave Configuration
        2. 7.4.7.2 Auto-Polarity Detection and Correction
      8. 7.4.8  MAC Interfaces
        1. 7.4.8.1 Reduced Gigabit Media Independent Interface
        2. 7.4.8.2 Serial Gigabit Media Independent Interface
      9. 7.4.9  Serial Management Interface
      10. 7.4.10 Direct Register Access
      11. 7.4.11 Extended Register Space Access
      12. 7.4.12 Write Address Operation
        1. 7.4.12.1 Example - Write Address Operation
      13. 7.4.13 Read Address Operation
        1. 7.4.13.1 Example - Read Address Operation
      14. 7.4.14 Write Operation (No Post Increment)
        1. 7.4.14.1 Example - Write Operation (No Post Increment)
      15. 7.4.15 Read Operation (No Post Increment)
        1. 7.4.15.1 Example - Read Operation (No Post Increment)
      16. 7.4.16 Write Operation (Post Increment)
        1. 7.4.16.1 Example - Write Operation (Post Increment)
      17. 7.4.17 Read Operation (Post Increment)
        1. 7.4.17.1 Example - Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 PHY Address Configuration
    6. 7.6 Register Maps
      1. 7.6.1 Register Access Summary
      2. 7.6.2 DP83TG720 Registers
        1. 7.6.2.1 Base Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
  9. 9 Power Supply Recommendations
  10. 10Compatibility with TI's 100BT1 PHY
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Physical Medium Attachment
      4. 11.1.4 Metal Pour
      5. 11.1.5 PCB Layer Stacking
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.1 Strap Configuration

The DP83TG720S-Q1 uses functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up and hardware reset (through either the RESET_N pin or register access). The strap pins support 2-levels and 3-levels, which are described in greater detail below. Configuration of the device may be done through strapping or through serial management interface.

Note:

  • Because strap pins are functional pins after reset is deasserted, they should not be connected directly to VCC or GND.
  • Pull up strap resistors are sufficient to enter different strap modes.
  • Pull down strap resistor can have application for LED pin straps. Refer to LED Configuration section.

GUID-20200910-CA0I-T8CB-CRGZ-5M1DGNNXJJ5L-low.gifFigure 7-18 Strap Circuit

Table 7-16 Recommended 3-level Strap Resistor Ratios
MODEIDEAL RH (kΩ)1
for VDDIO = 3.3 V		IDEAL RH (kΩ)2
for VDDIO = 2.5 V		IDEAL RH (kΩ)1
for VDDIO = 1.8V
1OPENOPENOPEN
213124
34.520.8
  1. 10% resistor accuracy
  2. 1% resistor accuracy
Table 7-17 Recommended 2-level Strap Resistor
MODEIDEAL RH (kΩ)12
1OPEN
22.49
  1. 10% resistor accuracy
  2. To gain more margin in customer application for 1.8V VDDIO, either 2.1K+/-10% pull-up can be used or resistor accuracy of 2.49K resistor can be limited to 1%.

The following table describes the DP83TG720S-Q1 configuration bootstraps:

Table 7-18 2-level Bootstraps
PIN NAMEPIN NO.STRAP MODESTRAP FUNCTIONDESCRIPTION
RX_D0261 (default)MAC[0] = 0MAC Interface Selection [0]. Refer to Table 7-19 for full description.
2MAC[0] = 1
RX_D1251 (default)MAC[1] = 0MAC Interface Selection [1]. Refer to Table 7-19 for full description.
2MAC[1] = 1
RX_D2241 (default)MAC[2] = 0MAC Interface Selection [2]. Refer to Table 7-19 for full description.
2MAC[2] = 1
LED_011 (default)MS = 0MDI Master Slave Select.
MS = 0 Slave
MS = 1 Master
2MS = 1
LED_161 (default)AUTO = 0Autonomous Disable
AUTO = 0 Autonomous
AUTO = 1 Managed
2AUTO = 1
Table 7-19 MAC Interface Selection Bootstraps
MAC[2]MAC[1]MAC[0]DESCRIPTION
000

SGMII (4-wire)

001RESERVED
010RESERVED
011RESERVED
100RGMII (Align Mode)
101RGMII (TX Shift Mode)
110RGMII (TX and RX Shift Mode)
111RGMII (RX Shift Mode)
Table 7-20 3-Level Bootstrap: PHY Address
PHY_AD[3:0]RX_CTRL
STRAP MODE		STRP_1
STRAP MODE		DESCRIPTION
000011PHY Address: 0x0000 (0)
0001--RESERVED
0010--RESERVED
0011--RESERVED
010021PHY Address: 0x0004 (4)
010131PHY Address: 0x0005 (5)
0110--RESERVED
0111--RESERVED
100012PHY Address: 0x0008 (8)
1001--RESERVED
101013PHY Address: 0x000A (10)
1011--RESERVED
110022PHY Address: 0x000C (12)
110132PHY Address: 0x000D (13)
111023PHY Address: 0x000E (14)
111133PHY Address: 0x000F (15)