SNLS777A May   2024  – June 2024 DP83TG721R-Q1 , DP83TG721S-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Device Comparison Table
  6. 5Application Information
    1. 5.1 Time Synchronization
    2. 5.2 Integrated Audio Over Ethernet
    3. 5.3 TC10 Sleep/Wake-Up
    4. 5.4 DP83TG721 EVM-MC and Software Support
    5. 5.5 Comparison of Device Features
  7. 6Device and Documentation Support
    1. 6.1 Receiving Notification of Documentation Updates
    2. 6.2 Support Resources
    3. 6.3 Trademarks
    4. 6.4 Electrostatic Discharge Caution
    5. 6.5 Glossary
  8. 7Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Description

The DP83TG721-Q1 is an IEEE 802.3bp and Open Alliance compliant automotive 1000Base-T1 Ethernet physical layer transceiver. The DP83TG721-Q1 provides all physical layer functions needed to transmit and receive data over unshielded/shielded single twisted-pair cables. The device provides xMII flexibility with support for RGMII and SGMII MAC interfaces.

DP83TG721-Q1 supports OA TC10 low power sleep feature (with wake forwarding) to reduce system power consumption when communication is not required. This device offers the Diagnostic Tool Kit, with an extensive list of real-time monitoring tools, debug tools and test modes.

DP83TG721-Q1 integrates IEEE 1588v2/802.1AS hardware time stamping & fractional PLL enabling highly accurate time synchronization. The fractional PLL enables frequency/phase synchronization of the Wall Clock eliminating need for external VCXO and generating wide range of time synchronized frequencies needed for Audio, Video and other ADAS applications.

DP83TG721-Q1 also integrates IEEE 1722 CRF decode to generate Media Clock (wall clock synchronized) for AVB & other Audio standards. The DP83TG721-Q1 is also capable of generating FSYNC/SCLK (wall clock synchronized) for I2S/TDM8 interface needed for audio applications.

The DP83TG721-Q1 is compatible to TI's 100BASE-T1 PHYs and 1000BASE-T1 PHYs enabling design scalability with single board for both speeds.

Device Information
PART NUMBERPACKAGE (1)BODY SIZE (NOM) (2)
DP83TG721R-Q1VQFN (36)6.00mm × 6.00mm
DP83TG721S-Q1VQFN (36)6.00mm × 6.00mm
For all available packages, see the orderable addendum at the end of the data sheet.
The package size (length × width) is a nominal value and includes pins, where applicable.
DP83TG721R-Q1 DP83TG721S-Q1 Simplified SchematicSimplified Schematic