Application software & framework
DP83TG721-Q1-DESIGN — DP83TG721-Q1 1000BASE-T1 PHY with TC-10 & IEEE 1588v2 / 802.1AS
DP83TG721-Q1
DP83TG721S-Q1
Automotive, 1000BASE-T1 Ethernet PHY with TC-10, 802.1AS, Advanced TSN and AVB features
Data sheet
DP83TG721S-Q1
- IEEE802.3bp 1000BASE-T1 compliant
- OA TC10 compliant, <20µA sleep current
- Local and remote wake up and wake forwarding
- Advanced TSN
- IEEE 1588v2/802.1AS Time Synchronization
- Hardware time-stamping with integrated phase correction
- Highly accurate 1pps signal (±15ns)
- Audio Clocking
- AVB IEEE 1722 media clock generation capability
- Phase synchronized wall clock output: 1KHz to 50MHz
- I2S & TDM8 SCLK/FSYNC/MCLK clock generation
- Open Alliance TC12 Interoperability and EMC compliant
- OA EMC compliant
- SAE J2962-3 EMC Compliant
- Integrated LPF on MDI pins
- MAC Interfaces: MII, RMII, RGMII, and SGMII
- Supported I/O voltages: 3.3V, 2.5V, and 1.8V
- Pin compatible with TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs
- Single board design for 100BASE-T1 and 1000BASE-T1 with required BOM change
- Diagnostic tool kit
- Temperature, Voltage, ESD monitor
- Data throughput calculator : Inbuilt MAC packet generator, counter and error checker
- Signal Quality Indicator
- TDR based open and short cable fault detection
- CQI for cable degradation monitoring
- Loopback modes
- AEC-Q100 Qualified
- IEC61000-4-2 ESD : ±8kV contact discharge
The DP83TG721-Q1 is an IEEE 802.3bp and Open Alliance compliant automotive 1000Base-T1 Ethernet physical layer transceiver. The DP83TG721-Q1 provides all physical layer functions needed to transmit and receive data over unshielded/shielded single twisted-pair cables. The device provides xMII flexibility with support for RGMII and SGMII MAC interfaces.
DP83TG721-Q1 supports OA TC10 low power sleep feature (with wake forwarding) to reduce system power consumption when communication is not required. This device offers the Diagnostic Tool Kit, with an extensive list of real-time monitoring tools, debug tools and test modes.
DP83TG721-Q1 integrates IEEE 1588v2/802.1AS hardware time stamping & fractional PLL enabling highly accurate time synchronization. The fractional PLL enables frequency/phase synchronization of the Wall Clock eliminating need for external VCXO and generating wide range of time synchronized frequencies needed for Audio, Video and other ADAS applications.
DP83TG721-Q1 also integrates IEEE 1722 CRF decode to generate Media Clock (wall clock synchronized) for AVB & other Audio standards. The DP83TG721-Q1 is also capable of generating FSYNC/SCLK (wall clock synchronized) for I2S/TDM8 interface needed for audio applications.
The DP83TG721-Q1 is compatible to TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs enabling design scalability with single board for both speeds.
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Technical documentation
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View all 5 | Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | DP83TG721x-Q1 1000BASE-T1 Automotive Ethernet PHY with Advanced TSN and AVB datasheet (Rev. A) | PDF | HTML | 10 Jun 2024 |
| Application brief | Advancing Humanoid Robotics with Single Pair Ethernet | PDF | HTML | 13 Dec 2024 | |
| Application note | SGMII Troubleshooting Guide | PDF | HTML | 05 Nov 2024 | |
| Application note | Basic Ethernet Interface Debug With Linux | PDF | HTML | 11 Oct 2024 | |
| Application note | How to Integrate Linux Driver Into Your System | PDF | HTML | 12 Jul 2024 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
Evaluation board
DP83TG721EVM-MC — DP83TG721 1000Base-T1 to 1000Base-T media converter evaluation module
The DP83TG721EVM-MC supports 1000Mbps speed and is IEEE 802.3bp compliant. This evaluation board is a media converter to enable bit-error rate testing and interoperability testing. There is an on-board MSP430F5529 for use with the USB-2-MDIO graphical user interface tool. DP83867 is provided for (...)
Driver or library
ETHERNET-SW — Ethernet PHY drivers & tools
The drivers for Texas Instruments' Ethernet physical layer (PHY) transceivers support communication through the serial management interface (MDC/MDIO) to configure and read PHY registers. Linux and RTOS drivers can be found on our github.
Simulation tool
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool
TINA-TI — SPICE-based analog simulation program
TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Reference designs
TIDA-020071 — TDA4 quad-automotive PHY RGMII reference design
This reference design interfaces with Jacinto™ 7 processor EVM boards through the RGMII Ethernet Expansion Connector. Four automotive Ethernet connections are added through TI's automotive Ethernet physical layers (PHY). This design shows an implementation with TI's DP83TC818S-Q1 100Mbps and (...)
Design guide: PDF
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RHA) | 36 | Ultra Librarian |
Ordering & quality
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