SPRS968F August   2016  – November 2019 DRA790 , DRA791 , DRA793 , DRA797

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  CSI2
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  HDQ1W
      10. 4.3.10 UART
      11. 4.3.11 McSPI
      12. 4.3.12 QSPI
      13. 4.3.13 McASP
      14. 4.3.14 USB
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 ATL
      25. 4.3.25 Emulation and Debug Subsystem
      26. 4.3.26 System and Miscellaneous
        1. 4.3.26.1 Sysboot
        2. 4.3.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.3.26.3 System Direct Memory Access (SDMA)
        4. 4.3.26.4 Interrupt Controllers (INTC)
      27. 4.3.27 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power on Hour (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS CSI2 DC Electrical Characteristics
      6. Table 5-11 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-12 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-13 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      USBPHY DC Electrical Characteristics
      10. 5.7.2      HDMIPHY DC Electrical Characteristics
      11. 5.7.3      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-14 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics for CBD Package
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.10.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RC On-die Oscillator Clock
        2. 5.10.4.2 Output Clocks
        3. 5.10.4.3 DPLLs, DLLs
          1. 5.10.4.3.1 DPLL Characteristics
          2. 5.10.4.3.2 DLL Characteristics
          3. 5.10.4.3.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  CSI2
          1. 5.10.6.6.1 CSI-2 MIPI D-PHY
        7. 5.10.6.7  EMIF
        8. 5.10.6.8  GPMC
          1. 5.10.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
        9. 5.10.6.9  Timers
        10. 5.10.6.10 I2C
          1. Table 5-56 Timing Requirements for I2C Input Timings
          2. Table 5-57 Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)
          3. Table 5-58 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        11. 5.10.6.11 HDQ1W
          1. 5.10.6.11.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.11.2 HDQ/1-Wire—1-Wire Mode
        12. 5.10.6.12 UART
          1. Table 5-63 Timing Requirements for UART
          2. Table 5-64 Switching Characteristics Over Recommended Operating Conditions for UART
        13. 5.10.6.13 McSPI
        14. 5.10.6.14 QSPI
        15. 5.10.6.15 McASP
          1. Table 5-71 Timing Requirements for McASP1
          2. Table 5-72 Timing Requirements for McASP2
          3. Table 5-73 Timing Requirements for McASP3/4/5/6/7/8
        16. 5.10.6.16 USB
          1. 5.10.6.16.1 USB1 DRD PHY
          2. 5.10.6.16.2 USB2 PHY
          3. 5.10.6.16.3 USB3 DRD ULPI—SDR—Slave Mode—12-pin Mode
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 DCAN
          1. Table 5-91 Timing Requirements for DCANx Receive
          2. Table 5-92 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-93 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-94 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-95 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-96 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-101 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-102 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-103 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-104 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-108 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-109 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-111 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 MLB
        21. 5.10.6.21 eMMC/SD/SDIO
          1. 5.10.6.21.1 MMC1—SD Card Interface
            1. 5.10.6.21.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.21.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.21.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.21.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.21.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.21.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.21.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.21.2 MMC2 — eMMC
            1. 5.10.6.21.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.21.2.2 High-speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.21.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
            4. 5.10.6.21.2.4 High-speed JC64 DDR, 8-bit data
              1. Table 5-142 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
          3. 5.10.6.21.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.21.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.21.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.21.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.21.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.21.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        22. 5.10.6.22 GPIO
        23. 5.10.6.23 PRU-ICSS
          1. 5.10.6.23.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.23.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-164 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-165 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.23.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-166 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.23.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-167 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-168 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.23.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-169 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-170 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-171 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.23.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.23.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-172 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-173 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-175 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-176 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.23.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.23.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-177 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-178 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-179 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.23.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-180 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-181 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-182 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-183 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.23.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-184 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-185 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.23.5 PRU-ICSS IOSETs
          6. 5.10.6.23.6 PRU-ICSS Manual Functional Mapping
        24. 5.10.6.24 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-202 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-203 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-204 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-205 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  IPU
    6. 6.6  PRU-ICSS
    7. 6.7  Memory Subsystem
      1. 6.7.1 EMIF
      2. 6.7.2 GPMC
      3. 6.7.3 ELM
      4. 6.7.4 OCMC
    8. 6.8  Interprocessor Communication
      1. 6.8.1 MailBox
      2. 6.8.2 Spinlock
    9. 6.9  Interrupt Controller
    10. 6.10 EDMA
    11. 6.11 Peripherals
      1. 6.11.1  VIP
      2. 6.11.2  DSS
      3. 6.11.3  Timers
        1. 6.11.3.1 General-Purpose Timers
        2. 6.11.3.2 32-kHz Synchronized Timer (COUNTER_32K)
        3. 6.11.3.3 Watchdog Timer
      4. 6.11.4  I2C
      5. 6.11.5  UART
        1. 6.11.5.1 UART Features
        2. 6.11.5.2 IrDA Features
        3. 6.11.5.3 CIR Features
      6. 6.11.6  McSPI
      7. 6.11.7  QSPI
      8. 6.11.8  McASP
      9. 6.11.9  USB
      10. 6.11.10 PCIe
      11. 6.11.11 DCAN
      12. 6.11.12 GMAC_SW
      13. 6.11.13 eMMC/SD/SDIO
      14. 6.11.14 GPIO
      15. 6.11.15 ePWM
      16. 6.11.16 eCAP
      17. 6.11.17 eQEP
    12. 6.12 On-chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 Power Regulators
        3. 7.5.2.3 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 PCIe Board Design and Layout Guidelines
        1. 7.5.5.1 PCIe Connections and Interface Compliance
          1. 7.5.5.1.1 Coupling Capacitors
          2. 7.5.5.1.2 Polarity Inversion
        2. 7.5.5.2 Non-standard PCIe connections
          1. 7.5.5.2.1 PCB Stackup Specifications
          2. 7.5.5.2.2 Routing Specifications
            1. 7.5.5.2.2.1 Impedance
            2. 7.5.5.2.2.2 Differential Coupling
            3. 7.5.5.2.2.3 Pair Length Matching
        3. 7.5.5.3 LJCB_REFN/P Connections
      6. 7.5.6 CSI2 Board Design and Routing Guidelines
        1. 7.5.6.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.6.1.1 General Guidelines
          2. 7.5.6.1.2 Length Mismatch Guidelines
            1. 7.5.6.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.6.1.3 Frequency-domain Specification Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR3 Board Design and Layout Guidelines
        1. 7.7.2.1  Board Designs
        2. 7.7.2.2  DDR3 EMIF
        3. 7.7.2.3  DDR3 Device Combinations
        4. 7.7.2.4  DDR3 Interface Schematic
          1. 7.7.2.4.1 32-Bit DDR3 Interface
          2. 7.7.2.4.2 16-Bit DDR3 Interface
        5. 7.7.2.5  Compatible JEDEC DDR3 Devices
        6. 7.7.2.6  PCB Stackup
        7. 7.7.2.7  Placement
        8. 7.7.2.8  DDR3 Keepout Region
        9. 7.7.2.9  Bulk Bypass Capacitors
        10. 7.7.2.10 High-Speed Bypass Capacitors
          1. 7.7.2.10.1 Return Current Bypass Capacitors
        11. 7.7.2.11 Net Classes
        12. 7.7.2.12 DDR3 Signal Termination
        13. 7.7.2.13 VREF_DDR Routing
        14. 7.7.2.14 VTT
        15. 7.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.2.15.1 Four DDR3 Devices
            1. 7.7.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.2.15.2 Two DDR3 Devices
            1. 7.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.2.15.3 One DDR3 Device
            1. 7.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.2.16 Data Topologies and Routing Definition
          1. 7.7.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.2.17 Routing Specification
          1. 7.7.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.2.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CBD|538
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.2 Pin Attributes

Table 4-1 describes the terminal characteristics and the signals multiplexed on each ball. The following list describes the table column headers:

  1. BALL NUMBER:This column lists ball numbers on the bottom side associated with each signal on the bottom.
  2. BALL NAME: This column lists mechanical name from package device (name is taken from muxmode 0).
  3. SIGNAL NAME:This column lists names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).

    4. NOTE

    Table 4-1 does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.3, Signal Descriptions.

    NOTE

    In driver off mode, the buffer is configured in high-impedance.

    NOTE

    In some cases Table 4-1 may present more than one signal name per muxmode for the same ball. First signal in the list is the dominant function as selected via CTRL_CORE_PAD_* register.

    All other signals are virtual functions that present alternate multiplexing options. This virtual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use this options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.

  4. Support: This column shows if the functionality is applicable for DRA790 / DRA791 / DRA793 devices. Note that the Pin Attributes table presents the functionality of DRA797 device. An empty box means "Yes".
  5. MUXMODE: Multiplexing mode number:
    1. MUXMODE 0 is the primary mode; this means that when MUXMODE=0 is set, the function mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily the default muxmode.

      2. NOTE

      The default mode is the mode at the release of the reset; also see the RESET REL. MUXMODE column.
    2. MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.
    3. An empty box means Not Applicable.
  6. TYPE: Signal type and direction:
    • I = Input
    • O = Output
    • IO = Input or Output
    • D = Open drain
    • DS = Differential Signaling
    • A = Analog
    • PWR = Power
    • GND = Ground
    • CAP = LDO Capacitor

    7. NOTE

    The RX buffer within the pad logic should be disabled on all pins that are not being used as an input. For more information, see the Control Module / Control Module Functional Description / PAD Functional Multiplexing and Configuration section in the device TRM.

  7. BALL RESET STATE: The state of the terminal at power-on reset:
    • drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated)
    • drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated)
    • OFF: High-impedance
    • PD: High-impedance with an active pulldown resistor
    • PU: High-impedance with an active pullup resistor
    • An empty box means Not Applicable

    8. NOTE

    Designs that contain pullup or pulldown resistors, either on the board or in attached devices that oppose internal pullup or pulldown resistors, that are active while the device is held in reset, must not remain in reset for long periods of time.
  8. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal)
    • drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated)
    • drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated)
    • drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated)
    • OFF: High-impedance
    • PD: High-impedance with an active pulldown resistor
    • PU: High-impedance with an active pullup resistor
    • An empty box means Not Applicable

    9. NOTE

    For more information on the CORE_PWRON_RET_RST reset signal and its reset sources, see the Power, Reset, and Clock Management / PRCM Reset Management Functional Description section of the Device TRM.
  9. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).
    An empty box means Not Applicable.
  10. IO VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply).
    An empty box means Not Applicable.
  11. POWER: The voltage supply that powers the terminal IO buffers.
    An empty box means Not Applicable.
  12. HYS: Indicates if the input buffer is with hysteresis:
    • Yes: With hysteresis
    • No: Without hysteresis
    • An empty box: Not Applicable

    13. NOTE

    For more information, see the hysteresis values in Section 5.7, Electrical Characteristics.
  13. BUFFER TYPE: Drive strength of the associated output buffer.
    An empty box means Not Applicable.

    14. NOTE

    For programmable buffer strength:

    • The default value is given in Table 4-1.
    • A note describes all possible values according to the selected muxmode.
  14. PULLUP / PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
    • PU: Internal pullup
    • PD: Internal pulldown
    • PU/PD: Internal pullup and pulldown
    • PUx/PDy: Programmable internal pullup and pulldown
    • PDy: Programmable internal pulldown
    • An empty box means No pull

    15. NOTE

    Internal pullup or pulldown resistors must be disabled when opposed by an external pullup or pulldown resistor on the board or within an attached device.

  15. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or logic "1") when the peripheral pin function is not selected by any of the PINCNTLx registers.
    • 0: Logic 0 driven on the peripheral's input signal port.
    • 1: Logic 1 driven on the peripheral's input signal port.
    • blank: Pin state driven on the peripheral's input signal port.

    16. NOTE

    Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (Hi-Z mode is not an input signal).

    NOTE

    When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided.

    NOTE

    Some of the EMIF1 signals have an additional state change at the release of porz. The state that the signals change to at the release of porz is as follows:

    drive 0 (OFF) for: ddr1_ck, ddr1_odt[0], ddr1_rst.

    drive 1 (OFF) for: ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_nck, ddr1_ba[2:0], ddr1_a[15:0], ddr1_csn[0], ddr1_cke, ddr1_dqm[3:0].

    NOTE

    Dual rank support is not available on this device, but signal names are retained for consistency with the DRA7xx family of devices.

Table 4-1 Pin Attributes(1)

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] Support [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET REL. MUXMODE [9] I/O VOLTAGE VALUE [10] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15]
F8 cap_vbbldo_dsp cap_vbbldo_dsp CAP
T7 cap_vbbldo_gpu cap_vbbldo_gpu CAP
G14 cap_vbbldo_iva cap_vbbldo_iva CAP
F17 cap_vbbldo_mpu cap_vbbldo_mpu CAP
U20 cap_vddram_core1 cap_vddram_core1 CAP
K7 cap_vddram_core3 cap_vddram_core3 CAP
G19 cap_vddram_core4 cap_vddram_core4 CAP
L7 cap_vddram_dsp cap_vddram_dsp CAP
V7 cap_vddram_gpu cap_vddram_gpu CAP
G12 cap_vddram_iva cap_vddram_iva CAP
G18 cap_vddram_mpu cap_vddram_mpu CAP
AC1 csi2_0_dx0 csi2_0_dx0 0 I 1.8 Yes LVCMOS CSI2 PU/PD
AD1 csi2_0_dx1 csi2_0_dx1 0 I 1.8 Yes LVCMOS CSI2 PU/PD
AE2 csi2_0_dx2 csi2_0_dx2 0 I 1.8 Yes LVCMOS CSI2 PU/PD
AB2 csi2_0_dy0 csi2_0_dy0 0 I 1.8 Yes LVCMOS CSI2 PU/PD
AC2 csi2_0_dy1 csi2_0_dy1 0 I 1.8 Yes LVCMOS CSI2 PU/PD
AD2 csi2_0_dy2 csi2_0_dy2 0 I 1.8 Yes LVCMOS CSI2 PU/PD
H23 dcan1_rx dcan1_rx 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
uart8_txd 2 O
mmc2_sdwp 3 I 0
hdmi1_cec 6 IO
gpio1_15 14 IO
Driver off 15 I
H22 dcan1_tx dcan1_tx 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
uart8_rxd 2 I 1
mmc2_sdcd 3 I 1
hdmi1_hpd 6 IO
gpio1_14 14 IO
Driver off 15 I
AC18 ddr1_a0 ddr1_a0 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE19 ddr1_a1 ddr1_a1 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD19 ddr1_a2 ddr1_a2 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB19 ddr1_a3 ddr1_a3 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD20 ddr1_a4 ddr1_a4 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE20 ddr1_a5 ddr1_a5 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA18 ddr1_a6 ddr1_a6 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA20 ddr1_a7 ddr1_a7 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y21 ddr1_a8 ddr1_a8 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC20 ddr1_a9 ddr1_a9 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA21 ddr1_a10 ddr1_a10 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC21 ddr1_a11 ddr1_a11 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC22 ddr1_a12 ddr1_a12 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC15 ddr1_a13 ddr1_a13 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB15 ddr1_a14 ddr1_a14 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC16 ddr1_a15 ddr1_a15 0 O PD drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE16 ddr1_ba0 ddr1_ba0 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA16 ddr1_ba1 ddr1_ba1 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB16 ddr1_ba2 ddr1_ba2 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD16 ddr1_casn ddr1_casn 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD21 ddr1_ck ddr1_ck 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB18 ddr1_cke ddr1_cke 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC19 ddr1_csn0 ddr1_csn0 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA23 ddr1_d0 ddr1_d0 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC24 ddr1_d1 ddr1_d1 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB24 ddr1_d2 ddr1_d2 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD24 ddr1_d3 ddr1_d3 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB23 ddr1_d4 ddr1_d4 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC23 ddr1_d5 ddr1_d5 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD23 ddr1_d6 ddr1_d6 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE24 ddr1_d7 ddr1_d7 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA24 ddr1_d8 ddr1_d8 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
W25 ddr1_d9 ddr1_d9 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y23 ddr1_d10 ddr1_d10 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD25 ddr1_d11 ddr1_d11 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AC25 ddr1_d12 ddr1_d12 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AB25 ddr1_d13 ddr1_d13 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AA25 ddr1_d14 ddr1_d14 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
W24 ddr1_d15 ddr1_d15 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
W23 ddr1_d16 ddr1_d16 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
U25 ddr1_d17 ddr1_d17 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
U24 ddr1_d18 ddr1_d18 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
W21 ddr1_d19 ddr1_d19 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
T22 ddr1_d20 ddr1_d20 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
U22 ddr1_d21 ddr1_d21 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
U23 ddr1_d22 ddr1_d22 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
T21 ddr1_d23 ddr1_d23 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
T23 ddr1_d24 ddr1_d24 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
T25 ddr1_d25 ddr1_d25 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
T24 ddr1_d26 ddr1_d26 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
P21 ddr1_d27 ddr1_d27 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
N21 ddr1_d28 ddr1_d28 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
P22 ddr1_d29 ddr1_d29 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
P23 ddr1_d30 ddr1_d30 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
P24 ddr1_d31 ddr1_d31 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE23 ddr1_dqm0 ddr1_dqm0 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
W22 ddr1_dqm1 ddr1_dqm1 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
U21 ddr1_dqm2 ddr1_dqm2 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
P25 ddr1_dqm3 ddr1_dqm3 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD22 ddr1_dqs0 ddr1_dqs0 0 IO PD PD 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
Y24 ddr1_dqs1 ddr1_dqs1 0 IO PD PD 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
V24 ddr1_dqs2 ddr1_dqs2 0 IO PD PD 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
R24 ddr1_dqs3 ddr1_dqs3 0 IO PD PD 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
AE22 ddr1_dqsn0 ddr1_dqsn0 0 IO PU PU 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
Y25 ddr1_dqsn1 ddr1_dqsn1 0 IO PU PU 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
V25 ddr1_dqsn2 ddr1_dqsn2 0 IO PU PU 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
R25 ddr1_dqsn3 ddr1_dqsn3 0 IO PU PU 1.35/1.5 vdds_ddr1 LVCMOS DDR PUx/PDy
AE21 ddr1_nck ddr1_nck 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD18 ddr1_odt0 ddr1_odt0 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AD17 ddr1_rasn ddr1_rasn 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
AE17 ddr1_rst ddr1_rst 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
Y20 ddr1_vref0 ddr1_vref0 0 PWR OFF drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR
AE18 ddr1_wen ddr1_wen 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS DDR PUx/PDy
C21 emu0 emu0 0 IO PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_30 14 IO
C22 emu1 emu1 0 IO PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_31 14 IO
E14 emu2 emu2 2 O PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
F14 emu3 emu3 2 O PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
F13 emu4 emu4 2 O PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
Y5 gpio6_10 gpio6_10 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
mdio_mclk 1 O 1
i2c3_sda 2 IO 1
usb3_ulpi_d7 3 IO 0
vin2b_hsync1 4 I
vin1a_clk0 9 I 0
ehrpwm2A 10 O
pr2_mii_mt1_clk No 11 I 0
pr2_pru0_gpi0 No 12 I
pr2_pru0_gpo0 No 13 O
gpio6_10 14 IO
Driver off 15 I
Y6 gpio6_11 gpio6_11 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD
mdio_d 1 IO 1
i2c3_scl 2 IO 1
usb3_ulpi_d6 3 IO 0
vin2b_vsync1 4 I
vin1a_de0 9 I 0
ehrpwm2B 10 O
pr2_mii1_txen No 11 O
pr2_pru0_gpi1 No 12 I
pr2_pru0_gpo1 No 13 O
gpio6_11 14 IO
Driver off 15 I
H21 gpio6_14 gpio6_14 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr8 1 IO 0
dcan2_tx 2 IO 1
uart10_rxd 3 I 1
i2c3_sda 9 IO 1
timer1 10 IO
gpio6_14 14 IO
Driver off 15 I
K22 gpio6_15 gpio6_15 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr9 1 IO 0
dcan2_rx 2 IO 1
uart10_txd 3 O
i2c3_scl 9 IO 1
timer2 10 IO
gpio6_15 14 IO
Driver off 15 I
K23 gpio6_16 gpio6_16 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr10 1 IO 0
clkout1 9 O
timer3 10 IO
gpio6_16 14 IO
Driver off 15 I
M1 gpmc_a0 gpmc_a0 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d16 2 I 0
vout3_d16 3 O
vin1b_d0 6 I 0
i2c4_scl 7 IO 1
uart5_rxd 8 I 1
gpio7_3
gpmc_a26
gpmc_a16 		14 IO
Driver off 15 I
M2 gpmc_a1 gpmc_a1 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d17 2 I 0
vout3_d17 3 O
vin1b_d1 6 I 0
i2c4_sda 7 IO 1
uart5_txd 8 O
gpio7_4 14 IO
Driver off 15 I
L2 gpmc_a2 gpmc_a2 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d18 2 I 0
vout3_d18 3 O
vin1b_d2 6 I 0
uart7_rxd 7 I 1
uart5_ctsn 8 I 1
gpio7_5 14 IO
Driver off 15 I
L1 gpmc_a3 gpmc_a3 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs2 1 O 1
vin1a_d19 2 I 0
vout3_d19 3 O
vin1b_d3 6 I 0
uart7_txd 7 O
uart5_rtsn 8 O
gpio7_6 14 IO
Driver off 15 I
K3 gpmc_a4 gpmc_a4 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs3 1 O 1
vin1a_d20 2 I 0
vout3_d20 3 O
vin1b_d4 6 I 0
i2c5_scl 7 IO 1
uart6_rxd 8 I 1
gpio1_26 14 IO
Driver off 15 I
K2 gpmc_a5 gpmc_a5 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d21 2 I 0
vout3_d21 3 O
vin1b_d5 6 I 0
i2c5_sda 7 IO 1
uart6_txd 8 O
gpio1_27 14 IO
Driver off 15 I
J1 gpmc_a6 gpmc_a6 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d22 2 I 0
vout3_d22 3 O
vin1b_d6 6 I 0
uart8_rxd 7 I 1
uart6_ctsn 8 I 1
gpio1_28 14 IO
Driver off 15 I
K1 gpmc_a7 gpmc_a7 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_d23 2 I 0
vout3_d23 3 O
vin1b_d7 6 I 0
uart8_txd 7 O
uart6_rtsn 8 O
gpio1_29 14 IO
Driver off 15 I
K4 gpmc_a8 gpmc_a8 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_hsync0 2 I 0
vout3_hsync 3 O
vin1b_hsync1 6 I 0
timer12 7 IO
spi4_sclk 8 IO 0
gpio1_30 14 IO
Driver off 15 I
H1 gpmc_a9 gpmc_a9 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_vsync0 2 I 0
vout3_vsync 3 O
vin1b_vsync1 6 I 0
timer11 7 IO
spi4_d1 8 IO 0
gpio1_31 14 IO
Driver off 15 I
J2 gpmc_a10 gpmc_a10 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_de0 2 I 0
vout3_de 3 O
vin1b_clk1 6 I 0
timer10 7 IO
spi4_d0 8 IO 0
gpio2_0 14 IO
Driver off 15 I
L3 gpmc_a11 gpmc_a11 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
vin1a_fld0 2 I 0
vout3_fld 3 O
vin1b_de1 6 I 0
timer9 7 IO
spi4_cs0 8 IO 1
gpio2_1 14 IO
Driver off 15 I
G1 gpmc_a12 gpmc_a12 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpmc_a0 5 O
vin1b_fld1 6 I 0
timer8 7 IO
spi4_cs1 8 IO 1
dma_evt1 9 I 0
gpio2_2 14 IO
Driver off 15 I
H3 gpmc_a13 gpmc_a13 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_rtclk 1 I 0
timer7 7 IO
spi4_cs2 8 IO 1
dma_evt2 9 I 0
gpio2_3 14 IO
Driver off 15 I
H4 gpmc_a14 gpmc_a14 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d3 1 IO 0
timer6 7 IO
spi4_cs3 8 IO 1
gpio2_4 14 IO
Driver off 15 I
K6 gpmc_a15 gpmc_a15 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d2 1 IO 0
timer5 7 IO
gpio2_5 14 IO
Driver off 15 I
K5 gpmc_a16 gpmc_a16 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d0 1 IO 0
gpio2_6 14 IO
Driver off 15 I
G2 gpmc_a17 gpmc_a17 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_d1 1 IO 0
gpio2_7 14 IO
Driver off 15 I
F2 gpmc_a18 gpmc_a18 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_sclk 1 IO
gpio2_8 14 IO
Driver off 15 I
A4(9) gpmc_a19 gpmc_a19 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat4 1 IO 1
gpmc_a13 2 O
vin2b_d0 6 I 0
gpio2_9 14 IO
Driver off 15 I
E7(9) gpmc_a20 gpmc_a20 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat5 1 IO 1
gpmc_a14 2 O
vin2b_d1 6 I 0
gpio2_10 14 IO
Driver off 15 I
D6(9) gpmc_a21 gpmc_a21 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat6 1 IO 1
gpmc_a15 2 O
vin2b_d2 6 I 0
gpio2_11 14 IO
Driver off 15 I
C5(9) gpmc_a22 gpmc_a22 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat7 1 IO 1
gpmc_a16 2 O
vin2b_d3 6 I 0
gpio2_12 14 IO
Driver off 15 I
B5 gpmc_a23 gpmc_a23 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_clk 1 IO 1
gpmc_a17 2 O
vin2b_d4 6 I 0
gpio2_13 14 IO
Driver off 15 I
D7(9) gpmc_a24 gpmc_a24 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat0 1 IO 1
gpmc_a18 2 O
vin2b_d5 6 I 0
gpio2_14 14 IO
Driver off 15 I
C6(9) gpmc_a25 gpmc_a25 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat1 1 IO 1
gpmc_a19 2 O
vin2b_d6 6 I 0
gpio2_15 14 IO
Driver off 15 I
A5(9) gpmc_a26 gpmc_a26 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat2 1 IO 1
gpmc_a20 2 O
vin2b_d7 6 I 0
gpio2_16 14 IO
Driver off 15 I
B6(9) gpmc_a27 gpmc_a27 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_dat3 1 IO 1
gpmc_a21 2 O
vin2b_hsync1 6 I
gpio2_17 14 IO
Driver off 15 I
F1 gpmc_ad0 gpmc_ad0 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d0 2 I 0
vout3_d0 3 O
gpio1_6 14 IO
sysboot0 15 I
E2 gpmc_ad1 gpmc_ad1 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d1 2 I 0
vout3_d1 3 O
gpio1_7 14 IO
sysboot1 15 I
E1 gpmc_ad2 gpmc_ad2 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d2 2 I 0
vout3_d2 3 O
gpio1_8 14 IO
sysboot2 15 I
C1 gpmc_ad3 gpmc_ad3 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d3 2 I 0
vout3_d3 3 O
gpio1_9 14 IO
sysboot3 15 I
D1 gpmc_ad4 gpmc_ad4 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d4 2 I 0
vout3_d4 3 O
gpio1_10 14 IO
sysboot4 15 I
D2 gpmc_ad5 gpmc_ad5 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d5 2 I 0
vout3_d5 3 O
gpio1_11 14 IO
sysboot5 15 I
B1 gpmc_ad6 gpmc_ad6 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d6 2 I 0
vout3_d6 3 O
gpio1_12 14 IO
sysboot6 15 I
B2 gpmc_ad7 gpmc_ad7 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d7 2 I 0
vout3_d7 3 O
gpio1_13 14 IO
sysboot7 15 I
C2 gpmc_ad8 gpmc_ad8 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d8 2 I 0
vout3_d8 3 O
gpio7_18 14 IO
sysboot8 15 I
D3 gpmc_ad9 gpmc_ad9 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d9 2 I 0
vout3_d9 3 O
gpio7_19 14 IO
sysboot9 15 I
A2 gpmc_ad10 gpmc_ad10 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d10 2 I 0
vout3_d10 3 O
gpio7_28 14 IO
sysboot10 15 I
B3 gpmc_ad11 gpmc_ad11 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d11 2 I 0
vout3_d11 3 O
gpio7_29 14 IO
sysboot11 15 I
C3 gpmc_ad12 gpmc_ad12 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d12 2 I 0
vout3_d12 3 O
gpio1_18 14 IO
sysboot12 15 I
C4 gpmc_ad13 gpmc_ad13 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d13 2 I 0
vout3_d13 3 O
gpio1_19 14 IO
sysboot13 15 I
A3 gpmc_ad14 gpmc_ad14 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d14 2 I 0
vout3_d14 3 O
gpio1_20 14 IO
sysboot14 15 I
B4 gpmc_ad15 gpmc_ad15 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d15 2 I 0
vout3_d15 3 O
gpio1_21 14 IO
sysboot15 15 I
H5 gpmc_advn_ale gpmc_advn_ale 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpmc_cs6 1 O
clkout2 2 O
gpmc_wait1 3 I 1
gpmc_a2 5 O
gpmc_a23 6 O
timer3 7 IO
i2c3_sda 8 IO 1
dma_evt2 9 I 0
gpio2_23
gpmc_a19 		14 IO
Driver off 15 I
H2 gpmc_ben0 gpmc_ben0 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpmc_cs4 1 O
vin2b_de1 6 I
timer2 7 IO
dma_evt3 9 I 0
gpio2_26
gpmc_a21 		14 IO
Driver off 15 I
H6 gpmc_ben1 gpmc_ben1 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpmc_cs5 1 O
vin2b_clk1 4 I
gpmc_a3 5 O
vin2b_fld1 6 I
timer1 7 IO
dma_evt4 9 I 0
gpio2_27
gpmc_a22 		14 IO
Driver off 15 I
L4 gpmc_clk gpmc_clk 0 IO PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 0
gpmc_cs7 1 O
clkout1 2 O
gpmc_wait1 3 I 1
vin2b_clk1 6 I
timer4 7 IO
i2c3_scl 8 IO 1
dma_evt1 9 I 0
gpio2_22
gpmc_a20 		14 IO
Driver off 15 I
F3 gpmc_cs0 gpmc_cs0 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpio2_19 14 IO
Driver off 15 I
A6 gpmc_cs1 gpmc_cs1 0 O PU PU 15 1.8/3.3 vddshv11 Yes Dual Voltage LVCMOS PU/PD
mmc2_cmd 1 IO 1
gpmc_a22 2 O
vin2b_vsync1 6 I
gpio2_18 14 IO
Driver off 15 I
G4 gpmc_cs2 gpmc_cs2 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs0 1 IO 1
gpio2_20
gpmc_a23
gpmc_a13 		14 IO
Driver off 15 I
G3 gpmc_cs3 gpmc_cs3 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs1 1 O 1
vin1a_clk0 2 I 0
vout3_clk 3 O
gpmc_a1 5 O
gpio2_21
gpmc_a24
gpmc_a14 		14 IO
Driver off 15 I
G5 gpmc_oen_ren gpmc_oen_ren 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpio2_24 14 IO
Driver off 15 I
F6 gpmc_wait0 gpmc_wait0 0 I PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD 1
gpio2_28
gpmc_a25
gpmc_a15 		14 IO
Driver off 15 I
G6 gpmc_wen gpmc_wen 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual Voltage LVCMOS PU/PD
gpio2_25 14 IO
Driver off 15 I
AE9 hdmi1_clockx hdmi1_clockx 0 O 1.8 vdda_hdmi HDMIPHY Pdy
AD10 hdmi1_clocky hdmi1_clocky 0 O 1.8 vdda_hdmi HDMIPHY Pdy
AE11 hdmi1_data0x hdmi1_data0x 0 O 1.8 vdda_hdmi HDMIPHY Pdy
AD12 hdmi1_data0y hdmi1_data0y 0 O 1.8 vdda_hdmi HDMIPHY Pdy
AE12 hdmi1_data1x hdmi1_data1x 0 O 1.8 vdda_hdmi HDMIPHY Pdy
AD13 hdmi1_data1y hdmi1_data1y 0 O 1.8 vdda_hdmi HDMIPHY Pdy
AE14 hdmi1_data2x hdmi1_data2x 0 O 1.8 vdda_hdmi HDMIPHY Pdy
AD15 hdmi1_data2y hdmi1_data2y 0 O 1.8 vdda_hdmi HDMIPHY Pdy
G22 i2c1_scl i2c1_scl 0 IO 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD
Driver off 15 I
G23 i2c1_sda i2c1_sda 0 IO 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD
Driver off 15 I
G21 i2c2_scl i2c2_scl 0 IO 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD 1
hdmi1_ddc_sda 1 IO
Driver off 15 I
F23 i2c2_sda i2c2_sda 0 IO 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS I2C PU/PD 1
hdmi1_ddc_scl 1 IO
Driver off 15 I
AB9 ljcb_clkn ljcb_clkn 0 IO 1.8 vdda_pcie LJCB
AC8 ljcb_clkp ljcb_clkp 0 IO 1.8 vdda_pcie LJCB
D16 mcasp1_aclkr mcasp1_aclkr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp7_axr2 1 IO 0
i2c4_sda 10 IO 1
gpio5_0 14 IO
Driver off 15 I
C16 mcasp1_aclkx mcasp1_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_fld0 7 I 0
i2c3_sda 10 IO 1
pr2_mdio_mdclk No 11 O
pr2_pru1_gpi7 No 12 I
pr2_pru1_gpo7 No 13 O
gpio7_31 14 IO
Driver off 15 I
D14 mcasp1_axr0 mcasp1_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
uart6_rxd 3 I 1
vin1a_vsync0 7 I 0
i2c5_sda 10 IO 1
pr2_mii0_rxer No 11 I 0
pr2_pru1_gpi8 No 12 I
pr2_pru1_gpo8 No 13 O
gpio5_2 14 IO
Driver off 15 I
B14 mcasp1_axr1 mcasp1_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
uart6_txd 3 O
vin1a_hsync0 7 I 0
i2c5_scl 10 IO 1
pr2_mii_mt0_clk No 11 I 0
pr2_pru1_gpi9 No 12 I
pr2_pru1_gpo9 No 13 O
gpio5_3 14 IO
Driver off 15 I
C14 mcasp1_axr2 mcasp1_axr2 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp6_axr2 1 IO 0
uart6_ctsn 3 I 1
gpio5_4 14 IO
Driver off 15 I
B15 mcasp1_axr3 mcasp1_axr3 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp6_axr3 1 IO 0
uart6_rtsn 3 O
gpio5_5 14 IO
Driver off 15 I
A15 mcasp1_axr4 mcasp1_axr4 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp4_axr2 1 IO 0
gpio5_6 14 IO
Driver off 15 I
A14 mcasp1_axr5 mcasp1_axr5 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp4_axr3 1 IO 0
gpio5_7 14 IO
Driver off 15 I
A17 mcasp1_axr6 mcasp1_axr6 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp5_axr2 1 IO 0
gpio5_8 14 IO
Driver off 15 I
A16 mcasp1_axr7 mcasp1_axr7 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp5_axr3 1 IO 0
timer4 10 IO
gpio5_9 14 IO
Driver off 15 I
A18 mcasp1_axr8 mcasp1_axr8 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp6_axr0 1 IO 0
spi3_sclk 3 IO 0
vin1a_d15 7 I 0
timer5 10 IO
pr2_mii0_txen No 11 O
pr2_pru1_gpi10 No 12 I
pr2_pru1_gpo10 No 13 O
gpio5_10 14 IO
Driver off 15 I
B17 mcasp1_axr9 mcasp1_axr9 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp6_axr1 1 IO 0
spi3_d1 3 IO 0
vin1a_d14 7 I 0
timer6 10 IO
pr2_mii0_txd3 No 11 O
pr2_pru1_gpi11 No 12 I
pr2_pru1_gpo11 No 13 O
gpio5_11 14 IO
Driver off 15 I
B16 mcasp1_axr10 mcasp1_axr10 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp6_aclkx 1 IO 0
mcasp6_aclkr 2 IO
spi3_d0 3 IO 0
vin1a_d13 7 I 0
timer7 10 IO
pr2_mii0_txd2 No 11 O
pr2_pru1_gpi12 No 12 I
pr2_pru1_gpo12 No 13 O
gpio5_12 14 IO
Driver off 15 I
B18 mcasp1_axr11 mcasp1_axr11 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp6_fsx 1 IO 0
mcasp6_fsr 2 IO
spi3_cs0 3 IO 1
vin1a_d12 7 I 0
timer8 10 IO
pr2_mii0_txd1 No 11 O
pr2_pru1_gpi13 No 12 I
pr2_pru1_gpo13 No 13 O
gpio4_17 14 IO
Driver off 15 I
A19 mcasp1_axr12 mcasp1_axr12 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp7_axr0 1 IO 0
spi3_cs1 3 IO 1
vin1a_d11 7 I 0
timer9 10 IO
pr2_mii0_txd0 No 11 O
pr2_pru1_gpi14 No 12 I
pr2_pru1_gpo14 No 13 O
gpio4_18 14 IO
Driver off 15 I
E17 mcasp1_axr13 mcasp1_axr13 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp7_axr1 1 IO 0
vin1a_d10 7 I 0
timer10 10 IO
pr2_mii_mr0_clk No 11 I 0
pr2_pru1_gpi15 No 12 I
pr2_pru1_gpo15 No 13 O
gpio6_4 14 IO
Driver off 15 I
E16 mcasp1_axr14 mcasp1_axr14 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp7_aclkx 1 IO 0
mcasp7_aclkr 2 IO
vin1a_d9 7 I 0
timer11 10 IO
pr2_mii0_rxdv No 11 I 0
pr2_pru1_gpi16 No 12 I
pr2_pru1_gpo16 No 13 O
gpio6_5 14 IO
Driver off 15 I
F16 mcasp1_axr15 mcasp1_axr15 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp7_fsx 1 IO 0
mcasp7_fsr 2 IO
vin1a_d8 7 I 0
timer12 10 IO
pr2_mii0_rxd3 No 11 I 0
pr2_pru0_gpi20 No 12 I
pr2_pru0_gpo20 No 13 O
gpio6_6 14 IO
Driver off 15 I
D17 mcasp1_fsr mcasp1_fsr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp7_axr3 1 IO 0
i2c4_scl 10 IO 1
gpio5_1 14 IO
Driver off 15 I
C17 mcasp1_fsx mcasp1_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_de0 7 I 0
i2c3_scl 10 IO 1
pr2_mdio_data No 11 IO 1
gpio7_30 14 IO
Driver off 15 I
E19 mcasp2_aclkx mcasp2_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d7 7 I 0
pr2_mii0_rxd2 No 11 I 0
pr2_pru0_gpi18 No 12 I
pr2_pru0_gpo18 No 13 O
Driver off 15 I
A20 mcasp2_axr0 mcasp2_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
Driver off 15 I
B19 mcasp2_axr1 mcasp2_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
Driver off 15 I
A21 mcasp2_axr2 mcasp2_axr2 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp3_axr2 1 IO 0
vin1a_d5 7 I 0
pr2_mii0_rxd0 No 11 I 0
pr2_pru0_gpi16 No 12 I
pr2_pru0_gpo16 No 13 O
gpio6_8 14 IO
Driver off 15 I
B21 mcasp2_axr3 mcasp2_axr3 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp3_axr3 1 IO 0
vin1a_d4 7 I 0
pr2_mii0_rxlink No 11 I 0
pr2_pru0_gpi17 No 12 I
pr2_pru0_gpo17 No 13 O
gpio6_9 14 IO
Driver off 15 I
B20 mcasp2_axr4 mcasp2_axr4 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp8_axr0 1 IO 0
gpio1_4 14 IO
Driver off 15 I
C19 mcasp2_axr5 mcasp2_axr5 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp8_axr1 1 IO 0
gpio6_7 14 IO
Driver off 15 I
D20 mcasp2_axr6 mcasp2_axr6 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp8_aclkx 1 IO 0
mcasp8_aclkr 2 IO
gpio2_29 14 IO
Driver off 15 I
C20 mcasp2_axr7 mcasp2_axr7 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp8_fsx 1 IO 0
mcasp8_fsr 2 IO
gpio1_5 14 IO
Driver off 15 I
D19 mcasp2_fsx mcasp2_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
vin1a_d6 7 I 0
pr2_mii0_rxd1 No 11 I 0
pr2_pru0_gpi19 No 12 I
pr2_pru0_gpo19 No 13 O
Driver off 15 I
A22 mcasp3_aclkx mcasp3_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp3_aclkr 1 IO
mcasp2_axr12 2 IO 0
uart7_rxd 3 I 1
vin1a_d3 7 I 0
pr2_mii0_crs No 11 I 0
pr2_pru0_gpi12 No 12 I
pr2_pru0_gpo12 No 13 O
gpio5_13 14 IO
Driver off 15 I
B22 mcasp3_axr0 mcasp3_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp2_axr14 2 IO 0
uart7_ctsn 3 I 1
uart5_rxd 4 I 1
vin1a_d1 7 I 0
pr2_mii1_rxer No 11 I 0
pr2_pru0_gpi14 No 12 I
pr2_pru0_gpo14 No 13 O
Driver off 15 I
B23 mcasp3_axr1 mcasp3_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp2_axr15 2 IO 0
uart7_rtsn 3 O
uart5_txd 4 O
vin1a_d0 7 I 0
pr2_mii1_rxlink No 11 I 0
pr2_pru0_gpi15 No 12 I
pr2_pru0_gpo15 No 13 O
Driver off 15 I
A23 mcasp3_fsx mcasp3_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp3_fsr 1 IO
mcasp2_axr13 2 IO 0
uart7_txd 3 O
vin1a_d2 7 I 0
pr2_mii0_col No 11 I 0
pr2_pru0_gpi13 No 12 I
pr2_pru0_gpo13 No 13 O
gpio5_14 14 IO
Driver off 15 I
C23 mcasp4_aclkx mcasp4_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp4_aclkr 1 IO
spi3_sclk 2 IO 0
uart8_rxd 3 I 1
i2c4_sda 4 IO 1
Driver off 15 I
A24 mcasp4_axr0 mcasp4_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
spi3_d0 2 IO 0
uart8_ctsn 3 I 1
uart4_rxd 4 I 1
i2c6_scl(10) 14 IO
Driver off 15 I
D23 mcasp4_axr1 mcasp4_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
spi3_cs0 2 IO 1
uart8_rtsn 3 O
uart4_txd 4 O
pr2_pru1_gpi0 No 12 I
pr2_pru1_gpo0 No 13 O
i2c6_sda(10) 14 IO
Driver off 15 I
B25 mcasp4_fsx mcasp4_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
mcasp4_fsr 1 IO
spi3_d1 2 IO 0
uart8_txd 3 O
i2c4_scl 4 IO 1
Driver off 15 I
AC3 mcasp5_aclkx mcasp5_aclkx 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 0
mcasp5_aclkr 1 IO
spi4_sclk 2 IO 0
uart9_rxd 3 I 1
i2c5_sda 4 IO 1
mlb_clk 5 I 1
pr2_pru1_gpi1 No 12 I
pr2_pru1_gpo1 No 13 O
Driver off 15 I
AA5 mcasp5_axr0 mcasp5_axr0 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 0
spi4_d0 2 IO 0
uart9_ctsn 3 I 1
uart3_rxd 4 I 1
mlb_sig 5 IO 1
pr2_mdio_mdclk No 11 O
pr2_pru1_gpi3 No 12 I
pr2_pru1_gpo3 No 13 O
Driver off 15 I
AC4 mcasp5_axr1 mcasp5_axr1 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 0
spi4_cs0 2 IO 1
uart9_rtsn 3 O
uart3_txd 4 O
mlb_dat 5 IO 1
pr2_mdio_data No 11 IO 1
pr2_pru1_gpi4 No 12 I
pr2_pru1_gpo4 No 13 O
Driver off 15 I
U6 mcasp5_fsx mcasp5_fsx 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 0
mcasp5_fsr 1 IO
spi4_d1 2 IO 0
uart9_txd 3 O
i2c5_scl 4 IO 1
pr2_pru1_gpi2 No 12 I
pr2_pru1_gpo2 No 13 O
Driver off 15 I
L6 mdio_d mdio_d 0 IO PU PU 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 1
uart3_ctsn 1 I 1
mii0_txer 3 O 0
vin2a_d0 4 I 0
vin1b_d0 5 I 0
pr1_mii0_rxlink No 11 I 0
pr2_pru1_gpi1 No 12 I
pr2_pru1_gpo1 No 13 O
gpio5_16 14 IO
Driver off 15 I
L5 mdio_mclk mdio_mclk 0 O PU PU 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 1
uart3_rtsn 1 O
mii0_col 3 I 0
vin2a_clk0 4 I
vin1b_clk1 5 I 0
pr1_mii0_col No 11 I 0
pr2_pru1_gpi0 No 12 I
pr2_pru1_gpo0 No 13 O
gpio5_15 14 IO
Driver off 15 I
U1 mlbp_clk_n mlbp_clk_n 0 I vdds_mlbp No BMLB18
U2 mlbp_clk_p mlbp_clk_p 0 I vdds_mlbp No BMLB18
T1 mlbp_dat_n mlbp_dat_n 0 IO OFF OFF vdds_mlbp No BMLB18
T2 mlbp_dat_p mlbp_dat_p 0 IO OFF OFF vdds_mlbp No BMLB18
U4 mlbp_sig_n mlbp_sig_n 0 IO OFF OFF vdds_mlbp No BMLB18
T3 mlbp_sig_p mlbp_sig_p 0 IO OFF OFF vdds_mlbp No BMLB18
U3 mmc1_clk mmc1_clk 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy 1
gpio6_21 14 IO
Driver off 15 I
V4 mmc1_cmd mmc1_cmd 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy 1
gpio6_22 14 IO
Driver off 15 I
V3 mmc1_dat0 mmc1_dat0 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy 1
gpio6_23 14 IO
Driver off 15 I
V2 mmc1_dat1 mmc1_dat1 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy 1
gpio6_24 14 IO
Driver off 15 I
W1 mmc1_dat2 mmc1_dat2 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy 1
gpio6_25 14 IO
Driver off 15 I
V1 mmc1_dat3 mmc1_dat3 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO2KV1833 Pux/PDy 1
gpio6_26 14 IO
Driver off 15 I
U5 mmc1_sdcd mmc1_sdcd 0 I PU PU 15 1.8/3.3 vddshv8 Yes Dual Voltage LVCMOS PU/PD 1
uart6_rxd 3 I 1
i2c4_sda 4 IO 1
gpio6_27 14 IO
Driver off 15 I
V5 mmc1_sdwp mmc1_sdwp 0 I PD PD 15 1.8/3.3 vddshv8 Yes Dual Voltage LVCMOS PU/PD 0
uart6_txd 3 O
i2c4_scl 4 IO 1
gpio6_28 14 IO
Driver off 15 I
Y2 mmc3_clk mmc3_clk 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
usb3_ulpi_d5 3 IO 0
vin2b_d7 4 I 0
vin1a_d7 9 I 0
ehrpwm2_tripzone_input 10 IO 0
pr2_mii1_txd3 No 11 O
pr2_pru0_gpi2 No 12 I
pr2_pru0_gpo2 No 13 O
gpio6_29 14 IO
Driver off 15 I
Y1 mmc3_cmd mmc3_cmd 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi3_sclk 1 IO 0
usb3_ulpi_d4 3 IO 0
vin2b_d6 4 I 0
vin1a_d6 9 I 0
eCAP2_in_PWM2_out 10 IO 0
pr2_mii1_txd2 No 11 O
pr2_pru0_gpi3 No 12 I
pr2_pru0_gpo3 No 13 O
gpio6_30 14 IO
Driver off 15 I
Y4 mmc3_dat0 mmc3_dat0 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi3_d1 1 IO 0
uart5_rxd 2 I 1
usb3_ulpi_d3 3 IO 0
vin2b_d5 4 I 0
vin1a_d5 9 I 0
eQEP3A_in 10 I 0
pr2_mii1_txd1 No 11 O
pr2_pru0_gpi4 No 12 I
pr2_pru0_gpo4 No 13 O
gpio6_31 14 IO
Driver off 15 I
AA2 mmc3_dat1 mmc3_dat1 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi3_d0 1 IO 0
uart5_txd 2 O
usb3_ulpi_d2 3 IO 0
vin2b_d4 4 I 0
vin1a_d4 9 I 0
eQEP3B_in 10 I 0
pr2_mii1_txd0 No 11 O
pr2_pru0_gpi5 No 12 I
pr2_pru0_gpo5 No 13 O
gpio7_0 14 IO
Driver off 15 I
AA3 mmc3_dat2 mmc3_dat2 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi3_cs0 1 IO 1
uart5_ctsn 2 I 1
usb3_ulpi_d1 3 IO 0
vin2b_d3 4 I 0
vin1a_d3 9 I 0
eQEP3_index 10 IO 0
pr2_mii_mr1_clk No 11 I 0
pr2_pru0_gpi6 No 12 I
pr2_pru0_gpo6 No 13 O
gpio7_1 14 IO
Driver off 15 I
W2 mmc3_dat3 mmc3_dat3 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi3_cs1 1 IO 1
uart5_rtsn 2 O
usb3_ulpi_d0 3 IO 0
vin2b_d2 4 I 0
vin1a_d2 9 I 0
eQEP3_strobe 10 IO 0
pr2_mii1_rxdv No 11 I 0
pr2_pru0_gpi7 No 12 I
pr2_pru0_gpo7 No 13 O
gpio7_2 14 IO
Driver off 15 I
Y3 mmc3_dat4 mmc3_dat4 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi4_sclk 1 IO 0
uart10_rxd 2 I 1
usb3_ulpi_nxt 3 I 0
vin2b_d1 4 I 0
vin1a_d1 9 I 0
ehrpwm3A 10 O
pr2_mii1_rxd3 No 11 I 0
pr2_pru0_gpi8 No 12 I
pr2_pru0_gpo8 No 13 O
gpio1_22 14 IO
Driver off 15 I
AA1 mmc3_dat5 mmc3_dat5 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi4_d1 1 IO 0
uart10_txd 2 O
usb3_ulpi_dir 3 I 0
vin2b_d0 4 I 0
vin1a_d0 9 I 0
ehrpwm3B 10 O
pr2_mii1_rxd2 No 11 I 0
pr2_pru0_gpi9 No 12 I
pr2_pru0_gpo9 No 13 O
gpio1_23 14 IO
Driver off 15 I
AA4 mmc3_dat6 mmc3_dat6 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi4_d0 1 IO 0
uart10_ctsn 2 I 1
usb3_ulpi_stp 3 O
vin2b_de1 4 I
vin1a_hsync0 9 I 0
ehrpwm3_tripzone_input 10 IO 0
pr2_mii1_rxd1 No 11 I 0
pr2_pru0_gpi10 No 12 I
pr2_pru0_gpo10 No 13 O
gpio1_24 14 IO
Driver off 15 I
AB1 mmc3_dat7 mmc3_dat7 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual Voltage LVCMOS PU/PD 1
spi4_cs0 1 IO 1
uart10_rtsn 2 O
usb3_ulpi_clk 3 I 0
vin2b_clk1 4 I
vin1a_vsync0 9 I 0
eCAP3_in_PWM3_out 10 IO 0
pr2_mii1_rxd0 No 11 I 0
pr2_pru0_gpi11 No 12 I
pr2_pru0_gpo11 No 13 O
gpio1_25 14 IO
Driver off 15 I
L24 nmin_dsp nmin_dsp 0 I PD PD 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
AE6 pcie_rxn0 pcie_rxn0 0 I OFF OFF 1.8 vdda_pcie SERDES
AD7 pcie_rxp0 pcie_rxp0 0 I OFF OFF 1.8 vdda_pcie SERDES
AE8 pcie_txn0 pcie_txn0 0 O 1.8 vdda_pcie SERDES
AD9 pcie_txp0 pcie_txp0 0 O 1.8 vdda_pcie SERDES
F19 porz porz 0 I 1.8/3.3 vddshv3 Yes IHHV1833 PU/PD
K24 resetn resetn 0 I PU PU 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
N2 rgmii0_rxc rgmii0_rxc 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 0
rmii1_txen 2 O
mii0_txclk 3 I 0
vin2a_d5 4 I 0
vin1b_d5 5 I 0
usb3_ulpi_d2 6 IO 0
pr1_mii_mt0_clk No 11 I 0
pr2_pru1_gpi11 No 12 I
pr2_pru1_gpo11 No 13 O
gpio5_26 14 IO
Driver off 15 I
P2 rgmii0_rxctl rgmii0_rxctl 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 0
rmii1_txd1 2 O
mii0_txd3 3 O
vin2a_d6 4 I 0
vin1b_d6 5 I 0
usb3_ulpi_d3 6 IO 0
pr1_mii0_txd3 No 11 O
pr2_pru1_gpi12 No 12 I
pr2_pru1_gpo12 No 13 O
gpio5_27 14 IO
Driver off 15 I
N4 rgmii0_rxd0 rgmii0_rxd0 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 0
rmii0_txd0 1 O
mii0_txd0 3 O
vin2a_fld0 4 I
vin1b_fld1 5 I 0
usb3_ulpi_d7 6 IO 0
pr1_mii0_txd0 No 11 O
pr2_pru1_gpi16 No 12 I
pr2_pru1_gpo16 No 13 O
gpio5_31 14 IO
Driver off 15 I
N3 rgmii0_rxd1 rgmii0_rxd1 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 0
rmii0_txd1 1 O
mii0_txd1 3 O
vin2a_d9 4 I 0
usb3_ulpi_d6 6 IO 0
pr1_mii0_txd1 No 11 O
pr2_pru1_gpi15 No 12 I
pr2_pru1_gpo15 No 13 O
gpio5_30 14 IO
Driver off 15 I
P1 rgmii0_rxd2 rgmii0_rxd2 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 0
rmii0_txen 1 O
mii0_txen 3 O
vin2a_d8 4 I 0
usb3_ulpi_d5 6 IO 0
pr1_mii0_txen No 11 O
pr2_pru1_gpi14 No 12 I
pr2_pru1_gpo14 No 13 O
gpio5_29 14 IO
Driver off 15 I
N1 rgmii0_rxd3 rgmii0_rxd3 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 0
rmii1_txd0 2 O
mii0_txd2 3 O
vin2a_d7 4 I 0
vin1b_d7 5 I 0
usb3_ulpi_d4 6 IO 0
pr1_mii0_txd2 No 11 O
pr2_pru1_gpi13 No 12 I
pr2_pru1_gpo13 No 13 O
gpio5_28 14 IO
Driver off 15 I
T4 rgmii0_txc rgmii0_txc 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
uart3_ctsn 1 I 1
rmii1_rxd1 2 I 0
mii0_rxd3 3 I 0
vin2a_d3 4 I 0
vin1b_d3 5 I 0
usb3_ulpi_clk 6 I 0
spi3_d0 7 IO 0
spi4_cs2 8 IO 1
pr1_mii0_rxd3 No 11 I 0
pr2_pru1_gpi5 No 12 I
pr2_pru1_gpo5 No 13 O
gpio5_20 14 IO
Driver off 15 I
T5 rgmii0_txctl rgmii0_txctl 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
uart3_rtsn 1 O
rmii1_rxd0 2 I 0
mii0_rxd2 3 I 0
vin2a_d4 4 I 0
vin1b_d4 5 I 0
usb3_ulpi_stp 6 O
spi3_cs0 7 IO 1
spi4_cs3 8 IO 1
pr1_mii0_rxd2 No 11 I 0
pr2_pru1_gpi6 No 12 I
pr2_pru1_gpo6 No 13 O
gpio5_21 14 IO
Driver off 15 I
R1 rgmii0_txd0 rgmii0_txd0 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_rxd0 1 I 0
mii0_rxd0 3 I 0
vin2a_d10 4 I 0
usb3_ulpi_d1 6 IO 0
spi4_cs0 7 IO 1
uart4_rtsn 8 O
pr1_mii0_rxd0 No 11 I 0
pr2_pru1_gpi10 No 12 I
pr2_pru1_gpo10 No 13 O
gpio5_25 14 IO
Driver off 15 I
R2 rgmii0_txd1 rgmii0_txd1 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_rxd1 1 I 0
mii0_rxd1 3 I 0
vin2a_vsync0 4 I
vin1b_vsync1 5 I 0
usb3_ulpi_d0 6 IO 0
spi4_d0 7 IO 0
uart4_ctsn 8 IO 1
pr1_mii0_rxd1 No 11 I 0
pr2_pru1_gpi9 No 12 I
pr2_pru1_gpo9 No 13 O
gpio5_24 14 IO
Driver off 15 I
P3 rgmii0_txd2 rgmii0_txd2 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_rxer 1 I 0
mii0_rxer 3 I 0
vin2a_hsync0 4 I
vin1b_hsync1 5 I 0
usb3_ulpi_nxt 6 I 0
spi4_d1 7 IO 0
uart4_txd 8 O
pr1_mii0_rxer No 11 I 0
pr2_pru1_gpi8 No 12 I
pr2_pru1_gpo8 No 13 O
gpio5_23 14 IO
Driver off 15 I
P4 rgmii0_txd3 rgmii0_txd3 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii0_crs 1 I 0
mii0_crs 3 I 0
vin2a_de0 4 I
vin1b_de1 5 I 0
usb3_ulpi_dir 6 I 0
spi4_sclk 7 IO 0
uart4_rxd 8 I 1
pr1_mii0_crs No 11 I 0
pr2_pru1_gpi7 No 12 I
pr2_pru1_gpo7 No 13 O
gpio5_22 14 IO
Driver off 15 I
P5 RMII_MHZ_50_CLK RMII_MHZ_50_CLK 0 IO PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 0
vin2a_d11 4 I 0
pr2_pru1_gpi2 No 12 I
pr2_pru1_gpo2 No 13 O
gpio5_17 14 IO
Driver off 15 I
E20 rstoutn rstoutn 0 O PD PD 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
K25 rtck rtck 0 O PU OFF 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_29 14 IO
B24 spi1_cs0 spi1_cs0 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
gpio7_10 14 IO
Driver off 15 I
C25 spi1_cs1 spi1_cs1 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
spi2_cs1 3 IO 1
gpio7_11 14 IO
Driver off 15 I
E24 spi1_cs2 spi1_cs2 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
uart4_rxd 1 I 1
mmc3_sdcd 2 I 1
spi2_cs2 3 IO 1
dcan2_tx 4 IO 1
mdio_mclk 5 O 1
hdmi1_hpd 6 IO
gpio7_12 14 IO
Driver off 15 I
E25 spi1_cs3 spi1_cs3 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
uart4_txd 1 O
mmc3_sdwp 2 I 0
spi2_cs3 3 IO 1
dcan2_rx 4 IO 1
mdio_d 5 IO 1
hdmi1_cec 6 IO
gpio7_13 14 IO
Driver off 15 I
D25 spi1_d0 spi1_d0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
gpio7_9 14 IO
Driver off 15 I
D24 spi1_d1 spi1_d1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
gpio7_8 14 IO
Driver off 15 I
C24 spi1_sclk spi1_sclk 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
gpio7_7 14 IO
Driver off 15 I
F24 spi2_cs0 spi2_cs0 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
uart3_rtsn 1 O
uart5_txd 2 O
gpio7_17 14 IO
Driver off 15 I
G24 spi2_d0 spi2_d0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
uart3_ctsn 1 I 1
uart5_rxd 2 I 1
gpio7_16 14 IO
Driver off 15 I
F25 spi2_d1 spi2_d1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
uart3_txd 1 O
gpio7_15 14 IO
Driver off 15 I
G25 spi2_sclk spi2_sclk 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 0
uart3_rxd 1 I 1
gpio7_14 14 IO
Driver off 15 I
K21 tclk tclk 0 I PU PU 0 1.8/3.3 vddshv3 Yes IQ1833 PU/PD
L23 tdi tdi 0 I PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_27 14 I
J20 tdo tdo 0 O PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
gpio8_28 14 IO
L21 tms tms 0 I PU PU 0 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
L22 trstn trstn 0 I PD PD 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
L20 uart1_ctsn uart1_ctsn 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 1
uart9_rxd 2 I 1
mmc4_clk 3 IO 1
gpio7_24 14 IO
Driver off 15 I
M24 uart1_rtsn uart1_rtsn 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart9_txd 2 O
mmc4_cmd 3 IO 1
gpio7_25 14 IO
Driver off 15 I
L25 uart1_rxd uart1_rxd 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 1
mmc4_sdcd 3 I 1
gpio7_22 14 IO
Driver off 15 I
M25 uart1_txd uart1_txd 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
mmc4_sdwp 3 I 0
gpio7_23 14 IO
Driver off 15 I
N22 uart2_ctsn uart2_ctsn 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 1
uart3_rxd 2 I 1
mmc4_dat2 3 IO 1
uart10_rxd 4 I 1
uart1_dtrn 5 O
gpio1_16 14 IO
Driver off 15 I
N24 uart2_rtsn uart2_rtsn 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart3_txd 1 O
uart3_irtx 2 O
mmc4_dat3 3 IO 1
uart10_txd 4 O
uart1_rin 5 I 1
gpio1_17 14 IO
Driver off 15 I
N23 uart2_rxd uart2_rxd 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 1
uart3_ctsn 1 I 1
uart3_rctx 2 O
mmc4_dat0 3 IO 1
uart2_rxd 4 I 1
uart1_dcdn 5 I 1
gpio7_26 14 IO
Driver off 15 I
N25 uart2_txd uart2_txd 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
uart3_rtsn 1 O
uart3_sd 2 O
mmc4_dat1 3 IO 1
uart2_txd 4 O
uart1_dsrn 5 I 0
gpio7_27 14 IO
Driver off 15 I
N5 uart3_rxd uart3_rxd 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD 1
rmii1_crs 2 I 0
mii0_rxdv 3 I 0
vin2a_d1 4 I 0
vin1b_d1 5 I 0
spi3_sclk 7 IO 0
pr1_mii0_rxdv No 11 I 0
pr2_pru1_gpi3 No 12 I
pr2_pru1_gpo3 No 13 O
gpio5_18 14 IO
Driver off 15 I
N6 uart3_txd uart3_txd 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual Voltage LVCMOS PU/PD
rmii1_rxer 2 I 0
mii0_rxclk 3 I 0
vin2a_d2 4 I 0
vin1b_d2 5 I 0
spi3_d1 7 IO 0
spi4_cs1 8 IO 1
pr1_mii_mr0_clk No 11 I 0
pr2_pru1_gpi4 No 12 I
pr2_pru1_gpo4 No 13 O
gpio5_19 14 IO
Driver off 15 I
AB7 usb1_dm usb1_dm 0 IO OFF OFF 3.3 vdda33v_usb1 USBPHY
AC6 usb1_dp usb1_dp 0 IO OFF OFF 3.3 vdda33v_usb1 USBPHY
AD3 usb1_drvvbus usb1_drvvbus 0 O PD PD 15 1.8/3.3 vdda33v_usb2 Yes Dual Voltage LVCMOS PU/PD
timer16 7 IO
gpio6_12 14 IO
Driver off 15 I
AC5 usb2_dm usb2_dm 0 IO 3.3 vdda33v_usb2 No USBPHY
AB6 usb2_dp usb2_dp 0 IO 3.3 vdda33v_usb2 No USBPHY
AA6 usb2_drvvbus usb2_drvvbus 0 O PD PD 15 1.8/3.3 vdda33v_usb2 Yes Dual Voltage LVCMOS PU/PD
timer15 7 IO
gpio6_13 14 IO
Driver off 15 I
AE5 usb_rxn0 usb_rxn0 0 I OFF OFF 1.8 vdda_usb1 SERDES
pcie_rxn1 1 I
AD6 usb_rxp0 usb_rxp0 0 I OFF OFF 1.8 vdda_usb1 SERDES
pcie_rxp1 1 I
AE3 usb_txn0 usb_txn0 0 O 1.8 vdda_usb1 SERDES
pcie_txn1 1 O
AD4 usb_txp0 usb_txp0 0 O 1.8 vdda_usb1 SERDES
pcie_txp1 1 O
J15, J16, J18, K12, K18, L12, L17, M11, M13, M15, M17, N11, N13, N15, N18, P10, P12, P14, P16, P18, R10, R12, R14, R16, R17, T11, T13, T15, T17, T9, U11, U13, U15, U18, U9, V10, V12, V14, V16, V18, W10, W12, W14, W16 vdd vdd PWR
F20 vpp vpp(11) PWR
AA10 vdda33v_usb1 vdda33v_usb1 PWR
Y10 vdda33v_usb2 vdda33v_usb2 PWR
L9 vdda_core_gmac vdda_core_gmac PWR
T6 vdda_csi vdda_csi PWR
R20 vdda_ddr vdda_ddr PWR
N10 vdda_debug vdda_debug PWR
K10, L10 vdda_dsp_iva vdda_dsp_iva PWR
N9 vdda_gpu vdda_gpu PWR
W15, Y15 vdda_hdmi vdda_hdmi PWR
K16, L16 vdda_mpu_abe vdda_mpu_abe PWR
W13, Y13 vdda_osc vdda_osc PWR
W11, Y11 vdda_pcie vdda_pcie PWR
M10 vdda_per vdda_per PWR
W8 vdda_usb1 vdda_usb1 PWR
Y8 vdda_usb2 vdda_usb2 PWR
Y9 vdda_usb3 vdda_usb3 PWR
K14, L14 vdda_video vdda_video PWR
G11, H20, W7, Y18 vdds18v vdds18v PWR
AA19, P20, Y19 vdds18v_ddr1 vdds18v_ddr1 PWR
G10, G9 vddshv1 vddshv1 PWR
G15, G17, H15, H17, J19, K19 vddshv3 vddshv3 PWR
M19, N19 vddshv4 vddshv4 PWR
U7, U8 vddshv7 vddshv7 PWR
N8, P8 vddshv8 vddshv8 PWR
M7, N7 vddshv9 vddshv9 PWR
J7, J8, K8 vddshv10 vddshv10 PWR
F7, G7, H7 vddshv11 vddshv11 PWR
T19, T20, V20, W17, W18, W20 vdds_ddr1 vdds_ddr1 PWR
P7, R7 vdds_mlbp vdds_mlbp PWR
H11, H13, H9, J11, J13, J9 vdd_dsp vdd_dsp PWR
D8 vin2a_clk0 vin2a_clk0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vout2_fld 4 O
emu5 5 O
kbd_row0 9 I 0
eQEP1A_in 10 I 0
pr1_edio_data_in0 No 12 I 0
pr1_edio_data_out0 No 13 O
gpio3_28
gpmc_a27
gpmc_a17 		14 IO
Driver off 15 I
C8 vin2a_d0 vin2a_d0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d23 4 O
emu10 5 O
uart9_ctsn 7 I 1
spi4_d0 8 IO 0
kbd_row4 9 I 0
ehrpwm1B 10 O
pr1_uart0_rxd No 11 I 1
pr1_edio_data_in5 No 12 I 0
pr1_edio_data_out5 No 13 O
gpio4_1 14 IO
Driver off 15 I
B9 vin2a_d1 vin2a_d1 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d22 4 O
emu11 5 O
uart9_rtsn 7 O
spi4_cs0 8 IO 1
kbd_row5 9 I 0
ehrpwm1_tripzone_input 10 IO 0
pr1_uart0_txd No 11 O
pr1_edio_data_in6 No 12 I 0
pr1_edio_data_out6 No 13 O
gpio4_2 14 IO
Driver off 15 I
A7 vin2a_d2 vin2a_d2 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d21 4 O
emu12 5 O
uart10_rxd 8 I 1
kbd_row6 9 I 0
eCAP1_in_PWM1_out 10 IO 0
pr1_ecap0_ecap_capin_apwm_o No 11 IO 0
pr1_edio_data_in7 No 12 I 0
pr1_edio_data_out7 No 13 O
gpio4_3 14 IO
Driver off 15 I
A9 vin2a_d3 vin2a_d3 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d20 4 O
emu13 5 O
uart10_txd 8 O
kbd_col0 9 O
ehrpwm1_synci 10 I 0
pr1_edc_latch0_in No 11 I 0
pr1_pru1_gpi0 No 12 I
pr1_pru1_gpo0 No 13 O
gpio4_4 14 IO
Driver off 15 I
A8 vin2a_d4 vin2a_d4 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d19 4 O
emu14 5 O
uart10_ctsn 8 I 1
kbd_col1 9 O
ehrpwm1_synco 10 O
pr1_edc_sync0_out No 11 O
pr1_pru1_gpi1 No 12 I
pr1_pru1_gpo1 No 13 O
gpio4_5 14 IO
Driver off 15 I
A11 vin2a_d5 vin2a_d5 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d18 4 O
emu15 5 O
uart10_rtsn 8 O
kbd_col2 9 O
eQEP2A_in 10 I 0
pr1_edio_sof No 11 O
pr1_pru1_gpi2 No 12 I
pr1_pru1_gpo2 No 13 O
gpio4_6 14 IO
Driver off 15 I
F10 vin2a_d6 vin2a_d6 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d17 4 O
emu16 5 O
mii1_rxd1 8 I 0
kbd_col3 9 O
eQEP2B_in 10 I 0
pr1_mii_mt1_clk No 11 I 0
pr1_pru1_gpi3 No 12 I
pr1_pru1_gpo3 No 13 O
gpio4_7 14 IO
Driver off 15 I
A10 vin2a_d7 vin2a_d7 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d16 4 O
emu17 5 O
mii1_rxd2 8 I 0
kbd_col4 9 O
eQEP2_index 10 IO 0
pr1_mii1_txen No 11 O
pr1_pru1_gpi4 No 12 I
pr1_pru1_gpo4 No 13 O
gpio4_8 14 IO
Driver off 15 I
B10 vin2a_d8 vin2a_d8 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d15 4 O
emu18 5 O
mii1_rxd3 8 I 0
kbd_col5 9 O
eQEP2_strobe 10 IO 0
pr1_mii1_txd3 No 11 O
pr1_pru1_gpi5 No 12 I
pr1_pru1_gpo5 No 13 O
gpio4_9
gpmc_a26 		14 IO
Driver off 15 I
E10 vin2a_d9 vin2a_d9 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vout2_d14 4 O
emu19 5 O
mii1_rxd0 8 I 0
kbd_col6 9 O
ehrpwm2A 10 O
pr1_mii1_txd2 No 11 O
pr1_pru1_gpi6 No 12 I
pr1_pru1_gpo6 No 13 O
gpio4_10
gpmc_a25 		14 IO
Driver off 15 I
D10 vin2a_d10 vin2a_d10 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
mdio_mclk 3 O 1
vout2_d13 4 O
kbd_col7 9 O
ehrpwm2B 10 O
pr1_mdio_mdclk No 11 O
pr1_pru1_gpi7 No 12 I
pr1_pru1_gpo7 No 13 O
gpio4_11
gpmc_a24 		14 IO
Driver off 15 I
C10 vin2a_d11 vin2a_d11 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
mdio_d 3 IO 1
vout2_d12 4 O
kbd_row7 9 I 0
ehrpwm2_tripzone_input 10 IO 0
pr1_mdio_data No 11 IO 1
pr1_pru1_gpi8 No 12 I
pr1_pru1_gpo8 No 13 O
gpio4_12
gpmc_a23 		14 IO
Driver off 15 I
B11 vin2a_d12 vin2a_d12 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
rgmii1_txc 3 O
vout2_d11 4 O
mii1_rxclk 8 I 0
kbd_col8 9 O
eCAP2_in_PWM2_out 10 IO 0
pr1_mii1_txd1 No 11 O
pr1_pru1_gpi9 No 12 I
pr1_pru1_gpo9 No 13 O
gpio4_13 14 IO
Driver off 15 I
D11 vin2a_d13 vin2a_d13 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
rgmii1_txctl 3 O
vout2_d10 4 O
mii1_rxdv 8 I 0
kbd_row8 9 I 0
eQEP3A_in 10 I 0
pr1_mii1_txd0 No 11 O
pr1_pru1_gpi10 No 12 I
pr1_pru1_gpo10 No 13 O
gpio4_14 14 IO
Driver off 15 I
C11 vin2a_d14 vin2a_d14 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
rgmii1_txd3 3 O
vout2_d9 4 O
mii1_txclk 8 I 0
eQEP3B_in 10 I 0
pr1_mii_mr1_clk No 11 I 0
pr1_pru1_gpi11 No 12 I
pr1_pru1_gpo11 No 13 O
gpio4_15 14 IO
Driver off 15 I
B12 vin2a_d15 vin2a_d15 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
rgmii1_txd2 3 O
vout2_d8 4 O
mii1_txd0 8 O
eQEP3_index 10 IO 0
pr1_mii1_rxdv No 11 I 0
pr1_pru1_gpi12 No 12 I
pr1_pru1_gpo12 No 13 O
gpio4_16 14 IO
Driver off 15 I
A12 vin2a_d16 vin2a_d16 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d7 2 I 0
rgmii1_txd1 3 O
vout2_d7 4 O
mii1_txd1 8 O
eQEP3_strobe 10 IO 0
pr1_mii1_rxd3 No 11 I 0
pr1_pru1_gpi13 No 12 I
pr1_pru1_gpo13 No 13 O
gpio4_24 14 IO
Driver off 15 I
A13 vin2a_d17 vin2a_d17 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d6 2 I 0
rgmii1_txd0 3 O
vout2_d6 4 O
mii1_txd2 8 O
ehrpwm3A 10 O
pr1_mii1_rxd2 No 11 I 0
pr1_pru1_gpi14 No 12 I
pr1_pru1_gpo14 No 13 O
gpio4_25 14 IO
Driver off 15 I
E11 vin2a_d18 vin2a_d18 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d5 2 I 0
rgmii1_rxc 3 I 0
vout2_d5 4 O
mii1_txd3 8 O
ehrpwm3B 10 O
pr1_mii1_rxd1 No 11 I 0
pr1_pru1_gpi15 No 12 I
pr1_pru1_gpo15 No 13 O
gpio4_26 14 IO
Driver off 15 I
F11 vin2a_d19 vin2a_d19 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d4 2 I 0
rgmii1_rxctl 3 I 0
vout2_d4 4 O
mii1_txer 8 O 0
ehrpwm3_tripzone_input 10 IO 0
pr1_mii1_rxd0 No 11 I 0
pr1_pru1_gpi16 No 12 I
pr1_pru1_gpo16 No 13 O
gpio4_27 14 IO
Driver off 15 I
B13 vin2a_d20 vin2a_d20 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d3 2 I 0
rgmii1_rxd3 3 I 0
vout2_d3 4 O
mii1_rxer 8 I 0
eCAP3_in_PWM3_out 10 IO 0
pr1_mii1_rxer No 11 I 0
pr1_pru1_gpi17 No 12 I
pr1_pru1_gpo17 No 13 O
gpio4_28 14 IO
Driver off 15 I
E13 vin2a_d21 vin2a_d21 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d2 2 I 0
rgmii1_rxd2 3 I 0
vout2_d2 4 O
mii1_col 8 I 0
pr1_mii1_rxlink No 11 I 0
pr1_pru1_gpi18 No 12 I
pr1_pru1_gpo18 No 13 O
gpio4_29 14 IO
Driver off 15 I
C13 vin2a_d22 vin2a_d22 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d1 2 I 0
rgmii1_rxd1 3 I 0
vout2_d1 4 O
mii1_crs 8 I 0
pr1_mii1_col No 11 I 0
pr1_pru1_gpi19 No 12 I
pr1_pru1_gpo19 No 13 O
gpio4_30 14 IO
Driver off 15 I
D13 vin2a_d23 vin2a_d23 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
vin2b_d0 2 I 0
rgmii1_rxd0 3 I 0
vout2_d0 4 O
mii1_txen 8 O
pr1_mii1_crs No 11 I 0
pr1_pru1_gpi20 No 12 I
pr1_pru1_gpo20 No 13 O
gpio4_31 14 IO
Driver off 15 I
B7 vin2a_de0 vin2a_de0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2a_fld0 1 I
vin2b_fld1 2 I
vin2b_de1 3 I
vout2_de 4 O
emu6 5 O
kbd_row1 9 I 0
eQEP1B_in 10 I 0
pr1_edio_data_in1 No 12 I 0
pr1_edio_data_out1 No 13 O
gpio3_29 14 IO
Driver off 15 I
C7 vin2a_fld0 vin2a_fld0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_clk1 2 I
vout2_clk 4 O
emu7 5 O
eQEP1_index 10 IO 0
pr1_edio_data_in2 No 12 I 0
pr1_edio_data_out2 No 13 O
gpio3_30
gpmc_a27
gpmc_a18 		14 IO
Driver off 15 I
E8 vin2a_hsync0 vin2a_hsync0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_hsync1 3 I
vout2_hsync 4 O
emu8 5 O
uart9_rxd 7 I 1
spi4_sclk 8 IO 0
kbd_row2 9 I 0
eQEP1_strobe 10 IO 0
pr1_uart0_cts_n No 11 I 1
pr1_edio_data_in3 No 12 I 0
pr1_edio_data_out3 No 13 O
gpio3_31
gpmc_a27 		14 IO
Driver off 15 I
B8 vin2a_vsync0 vin2a_vsync0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
vin2b_vsync1 3 I
vout2_vsync 4 O
emu9 5 O
uart9_txd 7 O
spi4_d1 8 IO 0
kbd_row3 9 I 0
ehrpwm1A 10 O
pr1_uart0_rts_n No 11 O
pr1_edio_data_in4 No 12 I 0
pr1_edio_data_out4 No 13 O
gpio4_0 14 IO
Driver off 15 I
A1, A25, AA13, AA15, AA7, AA8, AA9, AB8, AC13, AE1, AE15, AE25, G13, G16, G8, H10, H12, H14, H16, H18, H19, H8, J10, J12, J14, J17, K11, K13, K15, K17, K9, L11, L13, L15, L18, L8, M12, M14, M16, M18, M20, M8, M9, N12, N14, N16, N17, N20, P11, P13, P15, P17, P19, P9, R11, R13, R15, R18, R19, R8, R9, T10, T12, T14, T16, T18, T8, U10, U12, U14, U16, U17, U19, V11, V13, V15, V17, V19, V8, V9, W19, W9, Y14, Y16, Y17, Y7 vss vss GND
AA12 vssa_osc0 vssa_osc0 GND
AB11 vssa_osc1 vssa_osc1 GND
AC10 Wakeup0 dcan1_rx 1 I 15 1.8/3.3 vdda33v_usb1 Yes IHHV1833 PU/PD 1
gpio1_0
sys_nirq2 		14 I
Driver off 15 I
AB10 Wakeup3 sys_nirq1 1 I 15 1.8/3.3 vdda33v_usb1 Yes IHHV1833 PU/PD
gpio1_3
dcan2_rx 		14 I
Driver off 15 I
Y12 xi_osc0 xi_osc0 0 I 1.8 vdda_osc No LVCMOS Analog
AC11 xi_osc1 xi_osc1 0 I 1.8 vdda_osc No LVCMOS Analog
AB12 xo_osc0 xo_osc0 0 O 1.8 vdda_osc No LVCMOS Analog
AA11 xo_osc1 xo_osc1 0 A 1.8 vdda_osc No LVCMOS Analog
J25 xref_clk0 xref_clk0 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr8 1 IO 0
mcasp1_axr4 2 IO 0
mcasp1_ahclkx 3 O
mcasp5_ahclkx 4 O
atl_clk0 5 O
vin1a_d0 7 I 0
hdq0 8 IO 1
clkout2 9 O
timer13 10 IO
pr2_mii1_col No 11 I 0
pr2_pru1_gpi5 No 12 I
pr2_pru1_gpo5 No 13 O
gpio6_17 14 IO
Driver off 15 I
J24 xref_clk1 xref_clk1 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr9 1 IO 0
mcasp1_axr5 2 IO 0
mcasp2_ahclkx 3 O
mcasp6_ahclkx 4 O
atl_clk1 5 O
vin1a_clk0 7 I 0
timer14 10 IO
pr2_mii1_crs No 11 I 0
pr2_pru1_gpi6 No 12 I
pr2_pru1_gpo6 No 13 O
gpio6_18 14 IO
Driver off 15 I
H24 xref_clk2 xref_clk2 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr10 1 IO 0
mcasp1_axr6 2 IO 0
mcasp3_ahclkx 3 O
mcasp7_ahclkx 4 O
atl_clk2 5 O
timer15 10 IO
gpio6_19 14 IO
Driver off 15 I
H25 xref_clk3 xref_clk3 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
mcasp2_axr11 1 IO 0
mcasp1_axr7 2 IO 0
mcasp4_ahclkx 3 O
mcasp8_ahclkx 4 O
atl_clk3 5 O
hdq0 7 IO 1
clkout3 9 O
timer16 10 IO
gpio6_20 14 IO
Driver off 15 I
  1. NA in this table stands for Not Applicable.
  2. For more information on recommended operating conditions, see Section 5.4, Recommended Operating Conditions.
  3. The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA.
  4. The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40 Ω. For more information on DS[1:0] register configuration, see the Device TRM.
  5. IO drive strength for usb1_dp, usb1_dm, usb2_dp and usb2_dm: minimum 18.3 mA, maximum 89 mA (for a power supply vdda33v_usb1 and vdda33v_usb2 = 3.46 V).
  6. Minimum PU = 900 Ω, maximum PU = 3.090 kΩ and minimum PD = 14.25 kΩ, maximum PD = 24.8 kΩ.
    For more information, see chapter 7 of the USB2.0 specification, in particular section Signaling / Device Speed Identification.
  7. This function will not be supported on some pin-compatible roadmap devices. Pin compatibility can be maintained in the future by not using these GPIO signals.
  8. In PUx / PDy, x and y = 60 to 200 μA.
    The output impedance settings (or drive strengths) of this IO are programmable (34 Ω, 40 Ω, 48 Ω, 60 Ω, 80 Ω) depending on the values of the I[2:0] registers.
  9. The internal pull resistors for balls A4, E7, D6, C5, D7, C6, A5, B6 are permanently disabled when sysboot15 is set to 0 as described in the section Sysboot Configuration of the Device TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should be set to 1. If gpmc boot mode is used with SYSBOOT15=0 (not recommended) then external pull-downs should be implemented to keep the address bus at logic-1 value during boot since the gpmc ms-address bits are high-z during boot.
  10. I2C6 is not supported in TI standard software. I2C6 is not recommended for use to due to internal clock/reset dependencies on i2c1-5 and uart7.
  11. This signal is valid only for High-Security devices. For more details, see Section 5.8VPP Specification for One-Time Programmable (OTP) eFUSEs. For General Purpose devices do not connect any signal, test point, or board trace to this signal.