SLVSCP2F January 2015 – June 2020 DRV10975
PRODUCTION DATA.
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
HTSSOP | VQFN | |||
CPN | 3 | 24 | P | Charge pump pin 1, use a ceramic capacitor between CPN and CPP. |
CPP | 2 | 23 | P | Charge pump pin 2, use a ceramic capacitor between CPN and CPP. |
DIR | 14 | 11 | I | Direction |
FG | 12 | 9 | O | FG signal output |
GND | 8 | 5 | — | Digital and analog ground |
PGND | 15, 16 | 12, 13 | P | Power ground |
SCL | 10 | 7 | I | I2C clock signal |
SDA | 11 | 8 | I/O | I2C data signal |
SPEED | 13 | 10 | I | Speed control signal for PWM or analog input speed command
|
SW | 4 | 1 | O | Step-down regulator switching node output |
SWGND | 5 | 2 | P | Step-down regulator ground |
U | 17, 18 | 14, 15 | O | Motor U phase |
V | 19, 20 | 16, 17 | O | Motor V phase |
V1P8 | 7 | 4 | P | Internal 1.8-V digital core voltage. V1P8 capacitor must connect to GND. This is an output, but not specified to drive external loads. |
V3P3 | 9 | 6 | P | Internal 3.3-V supply voltage. V3P3 capacitor must connect to GND. This is an output and may drive external loads not to exceed IV3P3_MAX. |
VCC | 23, 24 | 20, 21 | P | Device power supply |
VCP | 1 | 22 | P | Charge pump output |
VREG | 6 | 3 | P | Step-down regulator output and feedback point |
W | 21, 22 | 18, 19 | O | Motor W phase |
Thermal pad (GND) | — | — | — | The exposed thermal pad must be electrically connected to ground plane through soldering to PCB for proper operation and connected to bottom side of PCB through vias for better thermal spreading. |