SLVSG18A January   2021  – December 2024 DRV3233-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Revision History
  6. 5Mechanical, Packaging, and Orderable Information
    1. 5.1 Package Option Addendum
    2. 5.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • AEC-Q100 qualified for automotive applications - Temperature options:
    • DRV3233EPHP: –40°C to +150°C, TA
    • DRV3233QPHP (Preview): –40°C to +125°C,TA
  • Functional Safety-Compliant targeted
    • Developed for functional safety applications
    • Documentation to aid ISO 26262 system design will be available
    • Systematic capability up to ASIL D targeted
  • Three phase half-bridge gate driver
    • Drives six N-channel MOSFETs (NMOS)
    • 4.5 to 60-V wide operating voltage range
    • Bootstrap architecture for high-side gate driver
    • Charge pump for 50mA average gate current
    • 100% PWM duty cycle support
    • Overdrive supply of external switches
  • Smart Gate Drive architecture
    • 45-level configurable peak gate drive current up to 1000 / 2000-mA (source / sink)
    • Three-step dynamic drive current control
    • Soft shutdown for power stage protection
  • Low-side Current Sense Amplifier
    • Sub-1 mV low input offset across temperature
    • 9-level adjustable gain
  • SPI-based detailed configuration and diagnostics
  • DRVOFF pin to disable driver independently
  • High voltage wake up pin (nSLEEP)
  • Multiple PWM interface options available
    • 6x, 3x, 1x PWM Modes
    • PWM over SPI
  • Supports 3.3-V, and 5-V Logic Inputs
  • Optional programmable OTP for reset settings
  • Advanced and configurable protection features
    • Battery and power supply voltage monitors
    • Phase feedback comparator
    • MOSFET VDS and Rsense over current monitors
    • Analog Built-In-Self-Test, Clock monitors
    • Fault condition indicator pin