SBAS639D October   2017  – June 2024 DRV5055-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Magnetic Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Magnetic Flux Direction
      2. 6.3.2 Magnetic Response
      3. 6.3.3 Sensitivity Linearity
      4. 6.3.4 Ratiometric Architecture
      5. 6.3.5 Operating VCC Ranges
      6. 6.3.6 Sensitivity Temperature Compensation for Magnets
      7. 6.3.7 Power-On Time
      8. 6.3.8 Hall Element Location
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Selecting the Sensitivity Option
      2. 7.1.2 Temperature Compensation for Magnets
      3. 7.1.3 Adding a Low-Pass Filter
      4. 7.1.4 Designing for Wire Break Detection
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1.4 Designing for Wire Break Detection

Some systems must detect if interconnect wires become open or shorted. The DRV5055-Q1 can support this function.

First, select a sensitivity option that causes the output voltage to stay within the VL range during normal operation. Second, add a pullup resistor between OUT and VCC. TI recommends a value between 20 kΩ to 100 kΩ, and the current through OUT must not exceed the IO specification, including current going into an external ADC. Then, if the output voltage is ever measured to be within 150 mV of VCC or GND, a fault condition exists. Figure 7-1 shows the circuit, and Table 7-1 describes fault scenarios.

DRV5055-Q1 Wire Fault Detection CircuitFigure 7-1 Wire Fault Detection Circuit
Table 7-1 Fault Scenarios and the Resulting VOUT
FAULT SCENARIOVOUT
VCC disconnectsClose to GND
GND disconnectsClose to VCC
VCC shorts to OUTClose to VCC
GND shorts to OUTClose to GND