DATA SHEET
DRV612 2-Vrms DirectPath Line Driver With Programmable-Fixed Gain
1 Features
- DirectPath™
- Eliminates Pops and Clicks
- Eliminates Output DC-Blocking Capacitors
- 3-V to 3.6-V Supply Voltage
- Low Noise and THD
- SNR > 105 dB at –1× Gain
- Vn < 12 μVms, 20 Hz to 20 kHz at –1× Gain (Typical)
- THD+N < 0.003% at 10-kΩ Load and –1× Gain
- 2-Vrms Output Voltage Into 600-Ω Load
- Single-Ended Input and Output
- Programmable Gain Select Reduces Component Count
- 13× Gain Values
- Active Mute With More Than 80-dB Attenuation
- Short-Circuit and Thermal Protection
- ±8-kV HBM ESD-Protected Outputs
2 Applications
- PDP and LCD TVs
- DVD Players
- Mini and Micro Combo Systems
- Soundcards
Functional Block Diagram
3 Description
The DRV612 is a single-ended, 2-Vrms stereo line driver designed to reduce component count, board space, and cost. It is ideal for single-supply electronics where size and cost are critical design parameters.
The DRV612 does not require a power supply greater than 3.3 V to generate its 5.6-VPP output, nor does it require a split-rail power supply.
The DRV612 device is designed using TI’s patented DirectPath technology, which integrates a charge pump to generate a negative supply rail that provides a clean, pop-free ground-biased output. The DRV612 is capable of driving 2 Vms into a 600-Ω load. DirectPath technology also allows the removal of the costly output dc-blocking capacitors.
The device has fixed-gain single-ended inputs with a gain-select pin. Using a single resistor on this pin, the designer can choose from 13 internal programmable gain settings to match the line driver with the codec output level. The device also reduces the component count and board space.
Line outputs have ±8-kV HBM ESD protection, enabling a simple ESD protection circuit. The DRV612 has built-in active mute control with more that 80-dB attenuation for pop-free mute on/off control.
The DRV612 is available in a 14-pin TSSOP and 16-pin VQFN. For a footprint-compatible stereo headphone driver, see the TPA6139A2.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| DRV612 | TSSOP (14) | 5.00 mm × 4.40 mm |
| VQFN (16) | 3.00 mm × 3.00 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
4 Revision History
Changes from B Revision (April 2011) to C Revision
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go
- Removed Ordering Information table, see POA at the end of the data sheet Go
Changes from A Revision (February 2011) to B Revision
- Changed RIN = 10 kΩ, Rfb = 20 kΩ To Gain = -2V/V in the Typical Characteristics condition textGo
Changes from * Revision (December 2010) to A Revision
- Added the QFN pinout drawingGo
- Added the QFN device to the Pin Functions tableGo
- Changed minimum storage temperature from –40°C to –65°CGo
- Changed the Gain resistor 2% tolerance values in the Programmable Gain Settings table for Gain Steps and Input ImpedanceGo
- Changed Note 1 of the PROGRAMMABLE GAIN SETTINGS table From: If pin 12, GAIN, is left floating To: If the GAIN pin is left floatingGo
- Changed From: CPUMP = C(VSS) = 10 µF To: CPUMP = C(VSS) = 1 µF in the Typical Characteristics condition textGo
- Changed the Gain_set RESISTOR values in Table 2Go
- Changed the Gain_set RESISTOR values in Table 3Go
- Removed references to DRV614 from the FOOTPRINT COMPATIBLE WITH TPA6139A2 sectionGo
5 Device Comparison Table
| GAIN | INPUT OFFSET (±) (uV) | Vmax (V) | Vmin (V) | PACKAGE (PIN) | |
|---|---|---|---|---|---|
| DRV603 | Adjustable | 1000 | 5.5 | 3 | TSSOP (14) |
| DRV604 | Adjustable | 500 | 3.7 | 3 | HTSSOP (28) |
| DRV612 | Adjustable | 1000 | 4 | 3 | TSSOP (14), VQFN (16) |
| DRV632 | Adjustable | 1000 | 4 | 3 | TSSOP (14) |
6 Pin Configuration and Functions
PW Package
14-Pin TSSOP
Top View
Pin Functions
| PIN | TYPE(1) | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | TSSOP | VQFN | ||
| –IN_L | 1 | 16 | I | Negative input, left channel |
| –IN_R | 14 | 13 | I | Negative input, right channel |
| CN | 6 | 6 | I/O | Charge Pump flying capacitor negative connection |
| CP | 9 | 8 | I/O | Charge Pump flying capacitor positive connection |
| GAIN | 12 | 11 | I | Gain set programming pin; connect a resistor to ground. See Table 2 for recommended resistor values. |
| GND | 3, 11 | 2, 3, 10 | P | Ground |
| MUTE | 4 | 4 | I | MUTE, active low |
| NC | 7, 8 | 7, 14, 15 | — | No internal connection |
| OUT_L | 2 | 1 | O | Output, left channel |
| OUT_R | 13 | 12 | O | Output, right channel |
| Thermal Pad | — | Thermal Pad | P | Connect to ground |
| VDD | 10 | 9 | P | Supply voltage, connect to positive supply |
| VSS | 5 | 5 | O | Change Pump negative supply voltage |
(1) I = Input, O = Output, P = Power
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| Voltage | Input, VI | VSS – 0.3 | VDD + 0.3 | V | |
| VDD to GND | –0.3 | 4 | |||
| MUTE to GND | –0.3 | VDD + 0.3 | |||
| Temperature | Maximum operating junction temperature, TJ | –40 | 150 | °C | |
| Storage temperature, Tstg | –65 | 150 | |||
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
| VALUE | UNIT | ||||
|---|---|---|---|---|---|
| DRV612 in the PW Package | |||||
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | All pins except Pins 2 and 13 | ±4000 | V |
| Pins 2 and 13 | ±8000 | ||||
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 | ||||
| DRV612 in the RGT Package | |||||
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | All pins except Pins 1 and 12 | ±4000 | V |
| Pins 1 and 12 | ±8000 | ||||
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 | ||||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range unless otherwise noted| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| VDD | Supply voltage, DC | 3 | 3.3 | 3.6 | V | |
| RL | Load resistance | 600 | 10000 | Ω | ||
| VIL | Low-level input voltage, MUTE | 38% | 40% | 43% | VDD | |
| VIH | High-level input voltage, MUTE | 57% | 60% | 66% | VDD | |
| TA | Free-air temperature | 0 | 25 | 85 | °C | |
7.4 Thermal Information
| THERMAL METRIC(1) | DRV612 | UNIT | ||
|---|---|---|---|---|
| PW (TSSOP) | RGT (VQFN) | |||
| 14 PINS | 16 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 130 | 52 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 49 | 71 | °C/W |
| RθJB | Junction-to-board thermal resistance | 63 | 26 | °C/W |
| ψJT | Junction-to-top characterization parameter | 3.6 | 3 | °C/W |
| ψJB | Junction-to-board characterization parameter | 62 | 26 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.5 Electrical Characteristics
VDD = 3.3 V, RLD = 5 kΩ, TA = 25°C, and charge pump (CCP) = 1 μF (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| |VOS| | Output offset voltage | VDD = 3.3 V, input ac-coupled | 0.5 | 1 | mV | |
| PSRR | Power-supply rejection ratio | 70 | 80 | dB | ||
| VOH | High-level output voltage | VDD = 3.3 V | 3.1 | V | ||
| VOL | Low-level output voltage | VDD = 3.3 V | –3.05 | V | ||
| Vuvp_on | VDD, undervoltage detection | 2.8 | V | |||
| Vuvp_hysteresis | VDD, undervoltage detection, hysteresis | 200 | mV | |||
| FCP | Charge-pump switching frequency | 350 | kHz | |||
| |IIH| | High-level input current, MUTE | VDD = 3.3 V, VIH = VDD | 1 | µA | ||
| |IIL| | Low-level input current, MUTE | VDD = 3.3 V, VIL = 0 V | 1 | µA | ||
| I(VDD) | Supply current, no load | VDD, MUTE = 3.3 V | 18 | mA | ||
| Supply current, MUTED | VDD = 3.3 V, MUTE = GND | 18 | mA | |||
| TSD | Thermal shutdown | 150 | °C | |||
| Thermal shutdown hysteresis | 15 | °C | ||||
7.6 Electrical Characteristics, Line Driver
VDD = 3.3 V, RLOAD = 10 kΩ, TA = 25°C, charge pump (CCP) = 1 µF, and 1× gain select (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VO | Output voltage, outputs in phase | 1% THD+N, f = 1 kHz, 10 -kΩ load | 2.2 | Vrms | ||
| THD+N | Total harmonic distortion plus noise | f = 1 kHz, 10-kΩ load, VO = 2 Vrms | 0.007% | |||
| SNR | Signal-to-noise ratio | A-weighted, AES17 filter, 2 Vrms ref | 105 | dB | ||
| DNR | Dynamic range | A-weighted, AES17 filter, 2 Vrms ref | 105 | dB | ||
| Vn | Noise voltage | A-weighted, AES17 filter | 12 | μV | ||
| Zo | Output impedance when muted | MUTE = GND | 0.07 | 1 | Ω | |
| Input-to-output attenuation when muted | 1 Vrms, 1-kHz input | 80 | dB | |||
| Slew rate | 4.5 | V/μs | ||||
| GBW | Unity-gain bandwidth | 8 | MHz | |||
| Crosstalk, line L-R and R-L | 10-kΩ load, VO = 2 Vrms | –91 | dB | |||
| Ilimit | Current limit | VDD = 3.3 V | 25 | mA | ||
7.7 Programmable Gain Settings
VDD = 3.3 V, Rload = 10 kΩ, TA = 25°C, Charge pump: CCP = 1 μF, 1× gain select (unless otherwise noted)(1)(2)(2) Gain setting is latched during power up.
7.8 Typical Characteristics
VDD = 3.3 V, TA = 25°C, RL = 2.5 kΩ, CPUMP = C(VSS) = 1 µF, and Gain = –2 V/V (unless otherwise noted)
Figure 1. THD+N vs Output Voltage 3.3 V, 10 kΩ, 1 kHz
Blue: 10-µF ceramic AC-coupling capacitor.
Red: 10-µF electrolytic AC-coupling capacitor.
Figure 3. THD+N vs Frequency 3.3 V, 10-kΩ Load, 2 Vrms
Red: 10-µF electrolytic AC-coupling capacitor.
Figure 5. Gain vs Frequency for the Different Gain Settings
Figure 7. Play to Mute
Figure 2. THD+N vs Output Voltage 3.3 V, 600-Ω Load, 1 kHz
Blue: L to R
Red: R to L
Figure 4. Channel Separation 3.3 V, 5-kΩ Load, 2 Vrms
Red: R to L
Figure 6. Mute to Play
