SLVSG22B January   2023  – March 2024 DRV8145-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 HW Variant
      1. 5.1.1 VQFN-HR(16) package
    2. 5.2 SPI Variant
      1. 5.2.1 HTSSOP (28) package
      2. 5.2.2 VQFN-HR(16) package
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1  Power Supply & Initialization
      2. 6.5.2  Logic I/Os
      3. 6.5.3  SPI I/Os
      4. 6.5.4  Configuration Pins - HW Variant Only
      5. 6.5.5  Power FET Parameters
      6. 6.5.6  Switching Parameters with High-Side Recirculation
      7. 6.5.7  Switching Parameters with Low-Side Recirculation
      8. 6.5.8  IPROPI & ITRIP Regulation
      9. 6.5.9  Over Current Protection (OCP)
      10. 6.5.10 Over Temperature Protection (TSD)
      11. 6.5.11 Voltage Monitoring
      12. 6.5.12 Load Monitoring
      13. 6.5.13 Fault Retry Setting
      14. 6.5.14 Transient Thermal Impedance & Current Capability
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Waveforms
      1. 6.7.1 Output switching transients
        1. 6.7.1.1 High-Side Recirculation
        2. 6.7.1.2 Low-Side Recirculation
      2. 6.7.2 Wake-up Transients
        1. 6.7.2.1 HW Variant
        2. 6.7.2.2 SPI Variant
      3. 6.7.3 Fault Reaction Transients
        1. 6.7.3.1 Retry setting
        2. 6.7.3.2 Latch setting
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 HW Variant
      2. 7.2.2 SPI Variant
    3. 7.3 Feature Description
      1. 7.3.1 External Components
        1. 7.3.1.1 HW Variant
        2. 7.3.1.2 SPI Variant
      2. 7.3.2 Bridge Control
        1. 7.3.2.1 Register - Pin Control - SPI Variant Only
      3. 7.3.3 Device Configuration
        1. 7.3.3.1 Slew Rate (SR)
        2. 7.3.3.2 IPROPI
        3. 7.3.3.3 ITRIP Regulation
        4. 7.3.3.4 DIAG
          1. 7.3.3.4.1 HW variant
          2. 7.3.3.4.2 SPI variant
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Over Current Protection (OCP)
        2. 7.3.4.2 Over Temperature Protection (TSD)
        3. 7.3.4.3 Off-State Diagnostics (OLP)
        4. 7.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
        5. 7.3.4.5 VM Over Voltage Monitor
        6. 7.3.4.6 VM Under Voltage Monitor
        7. 7.3.4.7 Charge pump under voltage monitor
        8. 7.3.4.8 Power On Reset (POR)
        9. 7.3.4.9 Event Priority
    4. 7.4 Programming - SPI Variant Only
      1. 7.4.1 SPI Interface
      2. 7.4.2 Standard Frame
      3. 7.4.3 SPI Interface for Multiple Peripherals
        1. 7.4.3.1 Daisy Chain Frame for Multiple Peripherals
  9. 8 Register Map - SPI Variant Only
    1. 8.1 User Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Load Summary
    2. 9.2 Typical Application
      1. 9.2.1 HW Variant
      2. 9.2.2 SPI Variant
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance Sizing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5.6 Switching Parameters with High-Side Recirculation

Load = 1.5mH / 4.7 Ohm, VVM = 13.5 V, refer high-side recirculation waveform

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SRLSOFF Output voltage rise time, 10% - 90% SR = 3'b000 or LVL2 1.5 V/µs
SR = 3'b001 (SPI only) 4.7 V/µs
SR = 3'b010 (SPI only) 9.6 V/µs
SR = 3'b011 or LVL3 14.4 V/µs
SR = 3'b100 or LVL4 20.6 V/µs
SR = 3'b101 or LVL1 26.5 V/µs
SR = 3'b110 or LVL6 37.9 V/µs
SR = 3'b111 or LVL5 47.1 V/µs
tPD_LSOFF Propagation time during output voltage rise SR = 3'b000 or LVL2 1.5 µs
SR = 3'b001 (SPI only) 0.9 µs
SR = 3'b010 (SPI only) 0.8 µs
SR = 3'b011 or LVL3 0.7 µs
SR = 3'b100 & 3'b101 or LVL4 & LVL1 0.6 µs
SR = 3'b110 & 3'b111 or LVL6 & LVL5 0.5 µs
tDEAD_LSOFF Dead time during output voltage rise All SRs 0.9 µs
SRLSON Output voltage fall time, 90% - 10% SR = 3'b000 or LVL2 1.5 V/µs
SR = 3'b001 (SPI only) 4.7 V/µs
SR = 3'b010 (SPI only) 9.6 V/µs
SR = 3'b011 or LVL3 14.4 V/µs
SR = 3'b100 or LVL4 20.6 V/µs
SR = 3'b101 or LVL1 26.5 V/µs
SR = 3'b110 or LVL6 37.9 V/µs
SR = 3'b111 or LVL5 47.1 V/µs
tPD_LSON Propagation time during output voltage fall SR = 3'b000 or LVL2 1.7 µs
SR = 3'b001 (SPI only) 0.9 µs
SR = 3'b010 (SPI only) 0.7 µs
SR = 3'b011 or LVL3 0.6 µs
SR = 3'b100 or LVL4 0.4 µs
SR = 3'b101 or LVL1 0.35 µs
SR = 3'b110 & 3'b111 or LVL6 & LVL5 0.3 µs
tDEAD_LSON Dead time during output voltage fall SR = 3'b000 or LVL2 2.7 µs
SR = 3'b001 (SPI only) 1.2 µs
SR = 3'b010 (SPI only) 0.9 µs
SR = 3'b011 or LVL3 0.8 µs
All other SRs 0.6 µs
MatchSRLS Output voltage rise and fall slew rate matching All SRs -20 +20 %