SLVSGZ1A May 2024 – July 2024 DRV8161 , DRV8162
ADVANCE INFORMATION
MIN | MAX | UNIT | ||
---|---|---|---|---|
Gate driver regulator pin voltage | GVDD, GVDD_LS | -0.3 | 20 | V |
High-side drain pin voltage | VDRAIN, TJ = 25℃ |
-0.3 | 102 | V |
Bootstrap pin voltage | BST, TJ = 25℃ |
-0.3 | 115 | V |
Bootstrap pin voltage | BST with respect to SH | -0.3 | 20 | V |
Logic pin voltage | nFAULT | -0.3 | 20 | V |
INH(IN), INL(EN), nDRVOFF, VDSLVL | -0.3 | 20 | ||
DT/MODE, IDRIVE1, IDRIVE2, CSAGAIN | -0.3 | 6 | ||
High-side gate drive pin voltage | GH, TJ = 25℃ GVDD >= 11V |
-5 | 115 | V |
High-side gate drive pin voltage | GH with respect to SH | -0.3 | 20 | V |
High-side source pin voltage | SH, DC | -5 | 105 | V |
Transient high-side source pin negative voltage | SH, 1 µs | -20 | V | |
High-side source pin slew rate | SH , VBST-SH >3.5V | 20 | V/ns | |
Low-side gate drive pin voltage | GL with respect to SL | -0.3 | 20 | V |
Low-side source sense pin voltage | SL | -5 | VGVDD+0.3 | V |
Transient low-side source sense pin negative voltage | SL, 1 µs | -16 | V | |
Current sense amplifier reference input pin voltage | CSAREF | -0.3 | 5.5 | V |
Shunt amplifier input pin voltage | SN, SP | -1 | 1 | V |
Transient 500-ns shunt amplifier input pin voltage | SN, SP, 500ns | -16 | 20 | V |
Shunt amplifier output pin voltage | SO | -0.3 | VCSAREF + 0.3 | V |
Junction temperature, TJ | –40 | 150 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |