SLVSGZ1B May   2024  – December 2024 DRV8161 , DRV8162

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 2-pin PWM Mode
          2. 7.3.1.1.2 1-pin PWM Mode
          3. 7.3.1.1.3 Independent PWM Mode
        2. 7.3.1.2 Gate Drive Architecture
          1. 7.3.1.2.1 Tickle Charge Pump (TCP)
          2. 7.3.1.2.2 Deadtime and Cross-Conduction Prevention (Shoot through protection)
      2. 7.3.2 Pin Diagrams
        1. 7.3.2.1 Four Level Input Pin (CSAGAIN)
        2. 7.3.2.2 Digital output nFAULT (DRV8162, DRV8162L)
        3. 7.3.2.3 Digital InOut nFAULT/nDRVOFF (DRV8161)
        4. 7.3.2.4 Multi-level inputs (IDRIVE1 and IDRIVE2)
        5. 7.3.2.5 Multi-level digital input (VDSLVL)
        6. 7.3.2.6 Multi-level digital input DT/MODE
      3. 7.3.3 Low-Side Current Sense Amplifiers
        1. 7.3.3.1 Bidirectional Current Sense Operation
      4. 7.3.4 Gate Driver Shutdown Sequence (nDRVOFF)
        1. 7.3.4.1 nDRVOFF Diagnostic
      5. 7.3.5 Gate Driver Protective Circuits
        1. 7.3.5.1 GVDD Undervoltage Lockout (GVDD_UV)
        2. 7.3.5.2 MOSFET VDS Overcurrent Protection (VDS_OCP)
        3. 7.3.5.3 Thermal Shutdown (OTSD)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with DRV8161
      2. 8.2.2 Typical Application with DRV8162 and DRV8162L
      3. 8.2.3 External Components
  10. 9 Layout
    1. 9.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2.4 Multi-level inputs (IDRIVE1 and IDRIVE2)

The DRV816x have IDRIVE1 and IDRIVE2 device pins for gate drive current configuration. Each pin can set 8 levels, LEVEL0 to LEVEL7, with an external resistor connected between the device pin and GND. The gate drive current IDRIVEN and IDRIVEP can be determined by Table 7-4. The (G) in the table indicates that VGS monitor dead time insertion is enabled. The IDRIVE1 and IDRIVE2 information are latched at the device power up.

DRV8161 DRV8162 Multi-level digital inputs of IDRIVE1 and IDRIVE2 Figure 7-11 Multi-level digital inputs of IDRIVE1 and IDRIVE2
Table 7-4 IDRIVE1/IDRIVE2 Truth Table for Gate Drive Current configuration
IDRIVE2 Input pin (RIDRIVE2)
LEVEL0 (Short to GND) LEVEL1 (2KΩ typ) LEVEL2 (5.6KΩ typ) LEVEL3 (12KΩ typ) LEVEL4 (27KΩ typ) LEVEL5 (62KΩ typ) LEVEL6 (130KΩ typ) LEVEL7 (Open)
Source:Sink = 1:2 Source:Sink = 1:2 Source:Sink = 1:1.5 Source:Sink = 1:1.5 Source:Sink = 1:1 Source:Sink = 1:3 VGS dead time insertion enabled IDRIVE2 open
IDRIVEP[mA] IDRIVEN[mA] IDRIVEP[mA] IDRIVEN[mA] IDRIVEP[mA] IDRIVEN[mA] IDRIVEP[mA] IDRIVEN[mA] IDRIVEP[mA] IDRIVEN[mA] IDRIVEP[mA] IDRIVEN[mA] IDRIVEP[mA] IDRIVEN[mA] IDRIVEP[mA] IDRIVEN[mA]
IDRIVE1 Input pin (RIDRIVE1) LEVEL7 (Open) 256 512 16 32 256 384 16 32 128 128 64 192 32 (G) 64 (G) 16 (G) 32 (G)
LEVEL6 (130KΩ typ) 288 576 32 64 288 448 32 32 192 192 128 384 96 (G) 192 (G) 64 (G) 128 (G)
LEVEL5 (62KΩ typ) 320 640 64 128 320 448 64 64 256 256 192 576 128 (G) 256 (G) 128 256
LEVEL4 (27KΩ typ) 384 768 96 192 384 576 96 128 320 320 256 768 160 (G) 320 (G) 192 384
LEVEL3 (12KΩ typ) 448 896 128 256 448 640 128 192 384 384 288 896 192 (G) 384 (G) 256 512
LEVEL2 (5.6KΩ typ) 512 1024 160 320 512 768 160 256 448 448 384 1024 224 (G) 448 (G) 320 640
LEVEL1 (2KΩ typ) 768 1536 192 384 768 1024 192 256 512 512 512 1536 512 (G) 1024 (G) 512 1024
LEVEL0 (Short to GND) 1024 2048 224 448 1024 1536 224 384 1024 1024 768 2048 1024 (G) 2048 (G) 1024 2048