SLVSGZ1B May   2024  – December 2024 DRV8161 , DRV8162

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 2-pin PWM Mode
          2. 7.3.1.1.2 1-pin PWM Mode
          3. 7.3.1.1.3 Independent PWM Mode
        2. 7.3.1.2 Gate Drive Architecture
          1. 7.3.1.2.1 Tickle Charge Pump (TCP)
          2. 7.3.1.2.2 Deadtime and Cross-Conduction Prevention (Shoot through protection)
      2. 7.3.2 Pin Diagrams
        1. 7.3.2.1 Four Level Input Pin (CSAGAIN)
        2. 7.3.2.2 Digital output nFAULT (DRV8162, DRV8162L)
        3. 7.3.2.3 Digital InOut nFAULT/nDRVOFF (DRV8161)
        4. 7.3.2.4 Multi-level inputs (IDRIVE1 and IDRIVE2)
        5. 7.3.2.5 Multi-level digital input (VDSLVL)
        6. 7.3.2.6 Multi-level digital input DT/MODE
      3. 7.3.3 Low-Side Current Sense Amplifiers
        1. 7.3.3.1 Bidirectional Current Sense Operation
      4. 7.3.4 Gate Driver Shutdown Sequence (nDRVOFF)
        1. 7.3.4.1 nDRVOFF Diagnostic
      5. 7.3.5 Gate Driver Protective Circuits
        1. 7.3.5.1 GVDD Undervoltage Lockout (GVDD_UV)
        2. 7.3.5.2 MOSFET VDS Overcurrent Protection (VDS_OCP)
        3. 7.3.5.3 Thermal Shutdown (OTSD)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with DRV8161
      2. 8.2.2 Typical Application with DRV8162 and DRV8162L
      3. 8.2.3 External Components
  10. 9 Layout
    1. 9.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

 VGVDD = 12 V VVDRAIN = 48 V TJ = 25℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (GVDD, BST)
IVDRAIN_UNPWR VDRAIN leakage current under GVDD unpowered  GVDD = 0V, VDRAIN = 48V, VBST-SH = 0V
Leakage current of VDRAIN + SH
 3.5 5 µA
IGVDD GVDD active mode current INH = INL = Switching @ 20kHz; VBST = VGVDD; NO FETs connected, DT/MODE Pin open.  VDS_LVL = 2V 2 mA
tWAKE Turnon time GVDD = 0V to 12V
GVDD_UV to active mode (outputs ready) (nFAULT = High)		 0.4 ms
ILBS_TCPON Bootstrap pin leakage current during high-side pull-up INH = high; TCP_ON 30 µA
LOGIC-LEVEL INPUTS (INH, INL, nDRVOFF)
VIL Input logic low voltage INL, INH, nDRVOFF 0.8 V
VIH Input logic high voltage INL, INH, nDRVOFF 2.2 V
RPU Input pullup resistance nDRVOFF to internal regulator, no external connection 250 kΩ
RPD Input pulldown resistance INH, INL to GND 250 kΩ
tnDRVOFF_DEG nDRVOFF input deglitch time DRVOFF falling and rising 1 2.1 4.2 µs
tnDRVOFF_DIAG nDRVOFF diagnostic pulse valid input time DRV8162 and DRV8162L only  0.5 µs
OPEN-DRAIN OUTPUT (nFAULT)
VOL Output logic low voltage IOD = 5 mA, GVDD > 4V 0.4 V
BOOTSTRAP DIODE (BST)
VBOOTD Bootstrap diode forward voltage IBOOT = 100 µA 0.82 V
VBOOTD Bootstrap diode forward voltage IBOOT = 100 mA 1.6 V
RBOOTD Bootstrap dynamic resistance (ΔVBOOTD/ΔIBOOT) IBOOT = 100 mA and 50 mA 3.9 4.8 9 Ω
CHARGE PUMP (BST)
VTCP Trickle charge pump output voltage VBST-SH , INH = High, SH = VDRAIN = 20V, BST > GVDD, External load ITRICKLE = 2uA 9.5 10.6 12 V
tTCP_DLY Trickle charge pump active delay time INL = Low 150 250 350 µs
GATE DRIVERS (GH, GL, SH, SL)
VGSHx_LO High-side gate drive low level voltage (VGH - VSH) IGHx = -10 mA; VGVDD = 12V; IDRIVE = 1000mA, No FETs connected 0 0.022 0.2 V
VGSHx_HI High-side gate drive high level voltage (VBST - VGH) IGHx = 10 mA; VGVDD = 12V; IDRIVE = 500mA, No FETs connected 0 0.09 0.2 V
VGSLx_LO Low-side gate drive low level voltage (VGL - VSL) IGLx = -10 mA; VGVDD = 12V; IDRIVE = 1000mA, No FETs connected 0 0.022 0.2 V
VGSLx_HI Low-side gate drive high level voltage (VGVDD - VGL) IGLx = 10 mA; VGVDD = 12V; IDRIVE = 500mA,  No FETs connected 0 0.09 0.2 V
IDRIVEP0 Peak source gate current VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 9 16 26 mA
IDRIVEP1 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 19 32 52 mA
IDRIVEP2 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 38 64 103 mA
IDRIVEP3 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 57 96 154 mA
IDRIVEP4 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 76 128 205 mA
IDRIVEP5 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 96 160 256 mA
IDRIVEP6 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 115 192 308 mA
IDRIVEP7 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 134 224 359 mA
IDRIVEP8 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 153 256 410 mA
IDRIVEP9 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 172 288 461 mA
IDRIVEP10 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 192 320 512 mA
IDRIVEP11 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 230 384 615 mA
IDRIVEP12 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 268 448 717 mA
IDRIVEP13 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 307 512 820 mA
IDRIVEP14 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 460 768 1229 mA
IDRIVEP15 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 614 1024 1639 mA
IDRIVEN0 Peak sink gate current VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 19 32 52 mA
IDRIVEN1 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 38 64 103 mA
IDRIVEN2 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 76 128 205 mA
IDRIVEN3 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 115 192 308 mA
IDRIVEN4 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 153 256 410 mA
IDRIVEN5 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 192 320 512 mA
IDRIVEN6 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 230 384 615 mA
IDRIVEN7 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 268 448 717 mA
IDRIVEN8 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 307 512 820 mA
IDRIVEN9 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 345 576 922 mA
IDRIVEN10 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 384 640 1024 mA
IDRIVEN11 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 460 768 1229 mA
IDRIVEN12 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 537 896 1434 mA
IDRIVEN13 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 614 1024 1639 mA
IDRIVEN14 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 921 1536 2458 mA
IDRIVEN15 VBST-VSH = VGVDD = 12V, TJ = -40℃ to 150℃ 1228 2048 3277 mA
RPD_LS Low-side passive pull down GL to SL, VGL - VSL = 2V 60 85 120 kΩ
RPDSA_HS High-side semiactive pull down VGVDD < VGVDD_UV 
GH to SH, VGH - VSH = 2V
 2 4 8 kΩ
IPUHOLD_HS High-side pull-up hold current TJ = -40℃ to 150℃ 307 512 820 mA
IPDHOLD_HS High-side pull-down hold current TJ = -40℃ to 150℃ 1228 2048 3277 mA
IPDSTRONG_LS Low-side pull-down strong current TJ = -40℃ to 150℃ 1228 2048 3277 mA
IPDSTRONG_HS High-side pull-down strong current TJ = -40℃ to 150℃ 1228 2048 3277 mA
IDRVIVENSD_LS Low-side peak sink gate shutdown current IDRIVENx is set to  IDRIVEN13 (1024mA  Typ) or smaller settings 32 mA
IDRVIVENSD_LS Low-side peak sink gate shutdown current IDRIVENx is set to IDRIVEN14 (1536mA  Typ) or IDRIVEN15 (2048mA  Typ) 64 mA
IDRIVENSD_HS High-side peak sink gate shutdown current IDRIVENx is set to  IDRIVEN13 (1024mA  Typ) or smaller settings 32 mA
IDRIVENSD_HS High-side peak sink gate shutdown current IDRIVENx is set to IDRIVEN14 (1536mA  Typ) or IDRIVEN15 (2048mA  Typ) 64 mA
GATE DRIVERS TIMINGS
tPDR_LS Low-side rising propagation delay INL to GL rising, VGVDD > 8V 25 40 80 ns
tPDF_LS Low-side falling propagation delay INL to GL falling, VGVDD > 8V 25 41 80 ns
tPDR_HS High-side rising propagation delay INH to GH rising, VGVDD = VBST - VSH > 8V
 25 41 80 ns
tPDF_HS High-side falling propagation delay INH to GH falling, VGVDD = VBST - VSH > 8V
 25 42 80 ns
tPD_MATCH Matching propagation delay of low-side gate driver GL turning ON to GL turning OFF, From VGL-SL = 1V to VGL-SL = VGVDD - 1V;  VGVDD = VBST - VSH > 8V; VSH = 0V to 90V, no load on GH and GL -8 ±4 8 ns
Matching propagation delay of high-side gate driver GH turning ON to GH turning OFF, From VGH-SH = 1V to VGH-SH = VBST-SH - 1V;  VGVDD = VBST - VSH > 8V; VSH = 0V to 90V, no load on GH and GL -10 ±4 10 ns
tPD_MATCH_PH Matching propagation delay per phase Deadtime disabled. GL turning OFF to GH turning ON, From VGL-SL = VGVDD - 1V to VGH-SH = 1V; VGVDD = VBST - VSH > 8V; VSH = 0V to 90V, no load on GH and GL, dead time disabled -12 ±4 12 ns
Deadtime disabled. GH turning OFF to GL turning ON, From VGH-SH = VBST-SH - 1V to VGL-SL = 1V ; VGVDD = VBST - VSH > 8V; VSH = 0V to 90V, no load on GH and GL -10 ±4 10 ns
tDEAD Gate drive dead time RDT = 470 Ω   2-pin PWM mode; 20 ns
tDEAD Gate drive dead time RDT = 1.3 KΩ   2-pin PWM mode; 97 100 120 ns
tDEAD Gate drive dead time RDT = 3.3 KΩ   2-pin PWM mode; 316 370 422 ns
tDEAD_CFG Gate drive dead time configuration range Tdead linear setting RDT = 10 KΩ- 1 MΩ, 1-pin PWM mode 
 20 900 ns
tDEAD Gate drive dead time RDT = 990 KΩ   1-pin PWM mode; TJ = -40℃ to 150℃ 700 900 1250 ns
tMINDEAD_VGS_HS Minimum gate drive dead time (shortest available) of VGS monitor mode; HS falling to LS rising VGS monitor dead time insertion mode.  tDEAD_CFG < 130ns, VGVDD > 8V, VBST-SH > 8V; 0V < VSH = <90V 215 ns
tMINDEAD_VGS_LS Minimum gate drive dead time (shortest available)  of VGS monitor mode; LS falling to HS rising VGS monitor dead time insertion; tDEAD_CFG < 130ns, VGVDD > 8V, VBST-SH > 8V; 0V < VSH = <90V 225 ns
tDRVN_SD Gate driver pulldown timing during shutdown 20 µs
CURRENT SHUNT AMPLIFIERS (SN, SO, SP, CSAREF)
ACSA Sense amplifier gain CSAGAIN = Tied to GND  (LEVEL0) 5 V/V
CSAGAIN = 10kΩ typ tied to GND (LEVEL1) 10 V/V
CSAGAIN = 30kΩ typ tied to GND (LEVEL2) 20 V/V
CSAGAIN = open;  (LEVEL3) 40 V/V
ACSA_ERR_DRIFT Sense amplifier gain error temperature drift TJ = -40℃ to 150℃ -70 70 ppm/℃
tSET Settling time to ±1% VSTEP = 1.6 V, ACSA = 5 V/V, CSO = 500pF 0.6 µs
VSTEP = 1.6 V, ACSA = 40 V/V, CSO = 500pF 0.8 µs
BW Bandwidth ACSA = 5 V/V, CLOAD = 60-pF, small signal -3 dB 3 5 7 MHz
VSWING Output voltage range VCSAREF = 3 to 5.5 V

 0.25 VCSAREF - 0.25 V
VCOM Common-mode input range -0.225 0.225 V
VOFF Input offset voltage VSP = VSN = GND; TJ = 25℃, Gain ACSA = 10, 20, 40 V/V
 -1.94 1.94 mV
VOFF Input offset voltage VSP = VSN = GND; TJ = 25℃, Gain ACSA = 5V/V -3.34 3.34 mV
VOFF_DRIFT Input drift offset voltage VSP = VSN = GND
 8 µV/℃
VBIAS Output voltage bias ratio VSP = VSN = GND 0.5
IBIAS Input bias current VSP = VSN = GND, VCSAREF = 3V to 5.5V 100 µA
IBIAS_OFF Input bias current offset ISP – ISN -1 1 µA
CMRR Common-mode rejection ratio DC 80 dB
20 kHz 60 dB
ICSA_SUP Supply current for CSA CSAREF, VCSAREF = 3.V to 5.5V 1.5 mA
TCMREC Common mode recovery time 2 us
PROTECTION CIRCUITS
VGVDD_UV GVDD undervoltage threshold VGVDD rising
 7.4 V
VGVDD falling 6.7 V
VGVDD_UV GVDD undervoltage threshold VGVDD rising, DRV8162L
 4.8 V
VGVDD falling, DRV8162L 4.7 V
tGVDD_UV_DG GVDD undervoltage deglitch time 5 10 15 µs
VBST_UV Bootstrap undervoltage threshold VBST - VSH; VBST rising, GVDD = 12V 7.43 V
Bootstrap undervoltage threshold VBST - VSH; VBST falling, GVDD = 12V  7.25 V
Bootstrap undervoltage threshold VBST - VSH; VBST rising, GVDD = 5V, DRV8162L
 4.08 V
Bootstrap undervoltage threshold VBST - VSH; VBST falling, GVDD = 5V, DRV8162L
 3.94 V
VDS_LVL0-0 VDS overcurrent protection threshold level (DC) RVDSLVL = 0.1 KΩ max (LEVEL0) 0.087 0.1 0.116 V
VDS_LVL1-1 RVDSLVL = 2 KΩ typ  (LEVEL1); one pulse detected on VDSLVL pin 0.138 0.15 0.166
VDS_LVL1-0 RVDSLVL = 2 KΩ typ (LEVEL1); DC 0.187 0.2 0.217
VDS_LVL2-1 RVDSLVL = 5.6 KΩ typ  (LEVEL2); one pulse detected on VDSLVL pin 0.286 0.3 0.319
VDS_LVL2-0 RVDSLVL = 5.6 KΩ typ (LEVEL2) 0.384 0.4 0.42
VDS_LVL3-1 RVDSLVL = 12 KΩ typ (LEVEL3); one pulse detected on VDSLVL pin 0.482 0.5 0.53
VDS_LVL3-0 RVDSLVL = 12 KΩ typ (LEVEL3) 0.575 0.6 0.623
VDS_LVL4-1 RVDSLVL = 26 KΩ typ (LEVEL4); one pulse detected on VDSLVL pin 0.67 0.7 0.73
VDS_LVL4-0 RVDSLVL = 26 KΩ typ (LEVEL4) 0.765 0.8 0.83
VDS_LVL5-1 RVDSLVL = 62 KΩ  typ (LEVEL5); one pulse detected on VDSLVL pin 0.87 0.9 0.93
VDS_LVL5-0 RVDSLVL = 62 KΩ typ (LEVEL5) 0.96 1.0 1.03
VDS_LVL6-1 RVDSLVL = 130 KΩ  typ (LEVEL6) ; one pulse detected on VDSLVL pin VDSLVL 1.46 1.5 1.545
VDS_LVL6-0 RVDSLVL = 130 KΩ  typ (LEVEL6); 1.945 2.0 2.05
tDS_DG VDS protection deglitch time  3 µs
tDS_BLK VDS overcurrent protection blanking time  1 µs
tCLRFLT VDS overcurrent protection fault clear time INH=INL=Low 250 µs
tVDSLVLFIL VDSLVL one pulse filter time 4 µs
VIHVDSLVL VDSLVL one pulse high-level detection voltage  1 V
TOTSD Thermal shutdown temperature TJ rising;  
 158 170 187 °C
THYS Thermal shutdown hysteresis 7 8.5 10 °C