SLVSFY8B February 2020 – August 2021 DRV8210
PRODUCTION DATA
In active mode, the H-bridge, charge pump, and internal logic are active and the device is ready to receive inputs. The device leaves active mode when entering low-power sleep mode or fault mode. When waking from autosleep, the INx pins (DRL package or DSG package when MODE = 0) or EN pin (DSG package when MODE = 1) must be held high for the duration of tWAKE to enable the device. After the tWAKE time has elapsed, the device is awake, and the INx pins or EN pin may receive a PWM signal.
When VVCC < VVM, the DRV8210 draws active current from the VM pin rather than the VCC pin. During this operating condition, IVCC is typically less than 500 nA (see Figure 7-5 and Figure 7-7.)