SLVSFY8B February 2020 – August 2021 DRV8210
PRODUCTION DATA
An analog current limit circuit on each MOSFET limits the peak current out of the device even in hard short circuit events. If the output current exceeds the overcurrent threshold, IOCP, for longer than the overcurrent deglitch time, tOCP, all MOSFETs in the H-bridge will be disabled. After tRETRY, the MOSFETs are re-enabled according to the state of the PH/IN1 and EN/IN2 pins. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes.
In half-bridge control mode, the OCP behavior is slightly modified. If an overcurrent event is detected, only the corresponding half-bridge will be disabled. The other half-bridge will continue normal operation. This allows for the device to manage independent fault events when driving independent loads. If an overcurrent event is detected in both half-bridges, both half-bridges will be disabled. Both half-bridges share the same overcurrent retry timer. If an overcurrent event occurs first in OUT1, that output will disable for the duration of tRETRY. If OUT2 experiences an overcurrent event after OUT1, but before tRETRY has expired, then both OUTx pins will remain disabled for a full duration of tRETRY.