SLVSGV9 august   2023 DRV8213

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Diagrams
    7. 7.7 Typical Operating Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 External Components
    4. 8.4 Feature Description
      1. 8.4.1 Bridge Control
      2. 8.4.2 Current Sense and Regulation (IPROPI)
        1. 8.4.2.1 Current Sensing and Current Mirror Gain Selection
        2. 8.4.2.2 Current Regulation
      3. 8.4.3 Hardware Stall Detection
      4. 8.4.4 Protection Circuits
        1. 8.4.4.1 Overcurrent Protection (OCP)
        2. 8.4.4.2 Thermal Shutdown (TSD)
        3. 8.4.4.3 VM Undervoltage Lockout (UVLO)
    5. 8.5 Device Functional Modes
      1. 8.5.1 Active Mode
      2. 8.5.2 Low-Power Sleep Mode
      3. 8.5.3 Fault Mode
    6. 8.6 Pin Diagrams
      1. 8.6.1 Logic-Level Inputs
      2. 8.6.2 Tri-Level Input
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Brushed DC Motor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Motor Voltage
          2. 9.2.1.2.2 Motor Current
        3. 9.2.1.3 Stall Detection
          1. 9.2.1.3.1 Detailed Design Procedure
            1. 9.2.1.3.1.1 Hardware Stall Detection Application Description
              1. 9.2.1.3.1.1.1 Hardware Stall Detection Timing
              2. 9.2.1.3.1.1.2 Hardware Stall Threshold Selection
            2. 9.2.1.3.1.2 Software Stall Detection Application Description
              1. 9.2.1.3.1.2.1 Software Stall Detection Timing
              2. 9.2.1.3.1.2.2 Software Stall Threshold Selection
        4. 9.2.1.4 Application Curves
        5. 9.2.1.5 Thermal Performance
          1. 9.2.1.5.1 Steady-State Thermal Performance
          2. 9.2.1.5.2 Transient Thermal Performance
  11. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.3 Hardware Stall Detection

The DRV8213 integrates a hardware stall detection feature available in the RTE package variant. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin (or 510 mV as applicable) to determine whether a stall condition has occurred. The following paragraphs describe how to configure the device pins for the desired stall detection response. For information on implementing stall detection in the DSG package variant, see Section 9.2.1.3.1.2.

The nSTALL output is pulled low when stall is detected. The nSTALL pin status is latched at power-up. It requires a pull-up resistor to VCC and pulls low when a stall condition occurs. This pin can be connected to the nFAULT pin so both pins share the same pullup resistor. Combining nFAULT and nSTALL signals reduces board area needed by external components and number of input pins on the controller to detect fault and stall conditions. By having separate pullup resistors for the nSTALL and nFAULT, the microcontroller can detect a device fault separate from a stall condtition using two input pins. Connecting nSTALL directly to GND disables stall detection. Table 8-5 summarizes the nSTALL pin settings.

Table 8-5 nSTALL configuration
nSTALLDescription
0 VStall detection disabled. Float TINRUSH. If IMODE = High-Z, current regulation will occur at all times when VIPROPI ≥ VVREF.
Pull-up resistor to VCCStall detection enabled. Pin pulls low to indicate a stall.

The IPROPI pin provides the current sense signal for the hardware stall detection feature. The VREF pin sets the ITRIP current level at which a stall condition is detected. For DSG package, or RTE package and SMODE = High-Z, VVREF is internally fixed at 510 mV. When VIPROPI ≥ VVREF, then IOUT ≥ ITRIP, and the device will detect a stall condition if the tINRUSH time has passed. The IPROPI and VREF pins are also responsible for current regulation, as described in Section 8.4.2.

The TINRUSH pin sets the amount of time that the stall detection scheme will ignore the inrush current during motor startup (tINRUSH). When the input pins transition from the state IN1 = IN2 = logic low to any other logic combination, the TINRUSH pin sources 10 μA of current into the capacitor (CINRUSH) connected from TINRUSH pin to ground. Once the voltage of the TINRUSH pin exceeds 1 V, the device discharges the capacitor in less than 100 μs. The capacitor charging time is internally multiplied by 65 to determine the tINRUSH time. After tINRUSH time expires, the DRV8213 indicates a stall condition the next time VIPROPI is greater than or equal to VVREF.

The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time -

  • Power-up of the DRV8213

  • Recovering from faults

  • After device exits from sleep mode

  • After recovering from stall, as explained in Table 8-6

Use the following formula to select the CINRUSH capacitor -

tINRUSH = 6.5 x 106 x CINRUSH

The SMODE pin sets the device's response to a stall condition. The device decides that a stall condtion has occurred when VIPROPI is greater than or equal to VVREF and the tINRUSH time has elapsed. When SMODE = logic low, the outputs disable, and the nSTALL pin latches low. When SMODE = logic high, the nSTALL pin still latches low, but the outputs continue to drive current into the motor. When SMODE = Hi-z, the device uses internal VVREF (510 mV) for stall detection, the nSTALL pin still latches low, but the outputs continue to drive current into the motor. Table 8-6 summarizes the SMODE pin settings.

Table 8-6 SMODE configuration
SMODEDescription

Recovery from Stall Condition

0Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low.To recover from this condition, device needs to enter sleep mode. nSTALL will go high after IN1 and IN2 are both low for tSLEEP. After waking up from sleep mode, the stall detection scheme ignores the inrush current for tINRUSH time.
1Indication only: the OUTx pins remain active and the nSTALL pin pulls low.

nSTALL goes high if stall condition is not observed and if IN1 and IN2 are both low for stall retry time (tSTALL_RETRY). After tINRUSH time, if motor current is still higher than ITRIP, nSTALL pin is pulled low again.

Hi-z

Indication only: the OUTx pins remain active and the nSTALL pin pulls low. Device uses internal VVREF (510 mV) for stall detection.

The stall retry time (tSTALL_RETRY) is implemented such that it is always lower than the autosleep turnoff time (tAUTOSLEEP).

The IMODE pin determines the behavior of current regulation in the motor driver. When IMODE is floating (IMODE = High-Z), the device only performs current regulation during the tINRUSH time. Table 8-4 summarizes the IMODE pin settings. For more details on current regulation, see Section 8.4.2.2.

The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature.

GUID-20220426-SS0I-VCC3-2HMD-PL52VGBRLQXK-low.svgFigure 8-7 Stall Detection with Latched Disable
GUID-20220426-SS0I-403Z-QZNJ-VHTFW7CB5NWB-low.svgFigure 8-8 Stall Detection with nSTALL indication only
GUID-20220426-SS0I-RMXN-XRG9-R5RZBRFPZGWD-low.svgFigure 8-9 Stall regulation with current regulation during inrush
GUID-20220426-SS0I-F3PC-TMFH-0ZJ2GVCX3VMQ-low.svgFigure 8-10 Stall detection with current regulation