SLVSG23C December   2021  – August 2022 DRV8243-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1. 6.1 HW Variant
      1. 6.1.1 HVSSOP (28) package
      2. 6.1.2 VQFN-HR (14) package
    2. 6.2 SPI Variant
      1. 6.2.1 HVSSOP (28) package
      2. 6.2.2 VQFN-HR (14) package
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
      1. 7.5.1  Power Supply & Initialization
      2. 7.5.2  Logic I/Os
      3. 7.5.3  SPI I/Os
      4. 7.5.4  Configuration Pins - HW Variant Only
      5. 7.5.5  Power FET Parameters
      6. 7.5.6  Switching Parameters with High-Side Recirculation
      7. 7.5.7  Switching Parameters with Low-Side Recirculation
      8. 7.5.8  IPROPI & ITRIP Regulation
      9. 7.5.9  Over Current Protection (OCP)
      10. 7.5.10 Over Temperature Protection (TSD)
      11. 7.5.11 Voltage Monitoring
      12. 7.5.12 Load Monitoring
      13. 7.5.13 Fault Retry Setting
      14. 7.5.14 Transient Thermal Impedance & Current Capability
    6. 7.6 SPI Timing Requirements
    7. 7.7 Switching Waveforms
      1. 7.7.1 Output switching transients
        1. 7.7.1.1 High-Side Recirculation
        2. 7.7.1.2 Low-Side Recirculation
      2. 7.7.2 Wake-up Transients
        1. 7.7.2.1 HW Variant
        2. 7.7.2.2 SPI Variant
      3. 7.7.3 Fault Reaction Transients
        1. 7.7.3.1 Retry setting
        2. 7.7.3.2 Latch setting
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 HW Variant
      2. 8.2.2 SPI Variant
    3. 8.3 Feature Description
      1. 8.3.1 External Components
        1. 8.3.1.1 HW Variant
        2. 8.3.1.2 SPI Variant
      2. 8.3.2 Bridge Control
        1. 8.3.2.1 PH/EN mode
        2. 8.3.2.2 PWM mode
        3. 8.3.2.3 Independent mode
        4. 8.3.2.4 Register - Pin Control - SPI Variant Only
      3. 8.3.3 Device Configuration
        1. 8.3.3.1 Slew Rate (SR)
        2. 8.3.3.2 IPROPI
        3. 8.3.3.3 ITRIP Regulation
        4. 8.3.3.4 DIAG
          1. 8.3.3.4.1 HW variant
          2. 8.3.3.4.2 SPI variant
      4. 8.3.4 Protection and Diagnostics
        1. 8.3.4.1 Over Current Protection (OCP)
        2. 8.3.4.2 Over Temperature Protection (TSD)
        3. 8.3.4.3 Off-State Diagnostics (OLP)
        4. 8.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
        5. 8.3.4.5 VM Over Voltage Monitor
        6. 8.3.4.6 VM Under Voltage Monitor
        7. 8.3.4.7 Power On Reset (POR)
        8. 8.3.4.8 Event Priority
    4. 8.4 Device Functional States
      1. 8.4.1 SLEEP State
      2. 8.4.2 STANDBY State
      3. 8.4.3 Wake-up to STANDBY State
      4. 8.4.4 ACTIVE State
      5. 8.4.5 nSLEEP Reset Pulse (HW Variant Only)
    5. 8.5 Programming - SPI Variant Only
      1. 8.5.1 SPI Interface
      2. 8.5.2 Standard Frame
      3. 8.5.3 SPI Interface for Multiple Peripherals
        1. 8.5.3.1 Daisy Chain Frame for Multiple Peripherals
    6. 8.6 Register Map - SPI Variant Only
      1. 8.6.1 User Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Load Summary
    2. 9.2 Typical Application
      1. 9.2.1 HW Variant
      2. 9.2.2 SPI Variant
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.4.3 Off-State Diagnostics (OLP)

The user can determine the impedance on the OUTx node using off-state diagnostics in the STANDBY state when the power FETs are off. With this diagnostics, it is possible to detect the following fault conditions passively in the STANDBY state:

  • Output short to VM or GND < 100 Ω
  • Open load > 1K Ω for full-bridge load or low-side load
  • Open load > 10K Ω for high-side load, VM = 13.5 V

Note: It is NOT possible to detect a load short with this diagnostic. However, the user can deduce this logically if an over current fault (OCP) occurs during ACTIVE operation, but OLP diagnostics do not report any fault in the STANDBY state. Occurrence of both OCP in the ACTIVE state and OLP in the STANDBY state would imply a terminal short (short on OUT node).

  • The user can configure the following combinations
    • Internal pull up resistor (ROLP_PU) on OUTx
    • Internal pull down resistor (ROLP_PD) on OUTx
    • Comparator reference level
    • Comparator input selection (OUT1 or OUT2)
  • This combination is determined by the controller inputs (pins only for the HW variant) or equivalent bits in the SPI_IN register for the SPI variant if the SPI_IN register has been unlocked.
  • HW variant - When off-state diagnostics are enabled, comparator output (OLP_CMP) is available on nFAULT pin.
  • SPI variant - The off-state diagnostics comparator output (OLP_CMP) is available on OLP_CMP bit in STATUS2 register. Additionally, if the SPI_IN register has been locked, this comparator output is also available on the nFAULT pin when off-state diagnostics are enabled.
  • The user is expected to toggle through all the combinations and record the comparator output after its output is settled.
  • Based on the input combinations and comparator output, the user can determine if there is a fault on the output.

Figure 8-6 Off-State Diagnostics for full-bridge Load (PH/EN or PWM Mode)

The OLP combinations and truth table for a no fault scenario vs. fault scenario for a full-bridge load in PH/EN or PWM modes is shown in Table 8-15.

Table 8-15 Off-State Diagnostics Table - PH/EN or PWM Mode (full-bridge)
User Inputs OLP Set-Up OLP CMP Output
nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 CMP REF Output selected Normal Open GND Short VM Short
1 1 1 0 ROLP_PU ROLP_PD VOLP_REFH OUT1 L H L H
1 1 0 1 ROLP_PU ROLP_PD VOLP_REFL OUT2 H L L H
1 1 1 1 ROLP_PD ROLP_PU VOLP_REFL OUT2 H H L H

The OLP combinations and truth table for a no fault scenario vs. fault scenario for a low-side load in Independent mode is shown in Table 8-16.

Table 8-16 Off-State Diagnostics Table for Low-Side Load - Independent Mode
User Inputs OLP Set-Up OLP_CMP Output
DIAG pin S_DIAG bits nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 CMP REF Output selected Normal Open Short
LVL2, LVL6 2'b01 1 1 1 don't care ROLP_PU Hi-Z VOLP_REFH OUT1 L H H
LVL3, LVL4 2'b11 1 1 1 don't care ROLP_PD Hi-Z VOLP_REFL OUT1 L L H
LVL2, LVL6 2'b01 1 1 0 1 Hi-Z ROLP_PU VOLP_REFH OUT2 L H H
LVL3, LVL4 2'b11 1 1 0 1 Hi-Z ROLP_PD VOLP_REFL OUT2 L L H

The OLP combinations and truth table for a no fault scenario vs. fault scenario for a high-side load in Independent mode is shown in Table 8-17.

Table 8-17 Off-State Diagnostics Table for High-Side Load - Independent Mode
User Inputs OLP Set-Up OLP_CMP Output
DIAG pin S_DIAG bits nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 CMP REF Output selected Normal Open Short
LVL2, LVL6 2'b01 1 1 1 don't care ROLP_PU Hi-Z VOLP_REFH OUT1 H H L
LVL3, LVL4 2'b11 1 1 1 don't care ROLP_PD Hi-Z VOLP_REFL OUT1 H L L
LVL2, LVL6 2'b01 1 1 0 1 Hi-Z ROLP_PU VOLP_REFH OUT2 H H L
LVL3, LVL4 2'b11 1 1 0 1 Hi-Z ROLP_PD VOLP_REFL OUT2 H L L