SLVSG23C December   2021  – August 2022 DRV8243-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1. 6.1 HW Variant
      1. 6.1.1 HVSSOP (28) package
      2. 6.1.2 VQFN-HR (14) package
    2. 6.2 SPI Variant
      1. 6.2.1 HVSSOP (28) package
      2. 6.2.2 VQFN-HR (14) package
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
      1. 7.5.1  Power Supply & Initialization
      2. 7.5.2  Logic I/Os
      3. 7.5.3  SPI I/Os
      4. 7.5.4  Configuration Pins - HW Variant Only
      5. 7.5.5  Power FET Parameters
      6. 7.5.6  Switching Parameters with High-Side Recirculation
      7. 7.5.7  Switching Parameters with Low-Side Recirculation
      8. 7.5.8  IPROPI & ITRIP Regulation
      9. 7.5.9  Over Current Protection (OCP)
      10. 7.5.10 Over Temperature Protection (TSD)
      11. 7.5.11 Voltage Monitoring
      12. 7.5.12 Load Monitoring
      13. 7.5.13 Fault Retry Setting
      14. 7.5.14 Transient Thermal Impedance & Current Capability
    6. 7.6 SPI Timing Requirements
    7. 7.7 Switching Waveforms
      1. 7.7.1 Output switching transients
        1. 7.7.1.1 High-Side Recirculation
        2. 7.7.1.2 Low-Side Recirculation
      2. 7.7.2 Wake-up Transients
        1. 7.7.2.1 HW Variant
        2. 7.7.2.2 SPI Variant
      3. 7.7.3 Fault Reaction Transients
        1. 7.7.3.1 Retry setting
        2. 7.7.3.2 Latch setting
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 HW Variant
      2. 8.2.2 SPI Variant
    3. 8.3 Feature Description
      1. 8.3.1 External Components
        1. 8.3.1.1 HW Variant
        2. 8.3.1.2 SPI Variant
      2. 8.3.2 Bridge Control
        1. 8.3.2.1 PH/EN mode
        2. 8.3.2.2 PWM mode
        3. 8.3.2.3 Independent mode
        4. 8.3.2.4 Register - Pin Control - SPI Variant Only
      3. 8.3.3 Device Configuration
        1. 8.3.3.1 Slew Rate (SR)
        2. 8.3.3.2 IPROPI
        3. 8.3.3.3 ITRIP Regulation
        4. 8.3.3.4 DIAG
          1. 8.3.3.4.1 HW variant
          2. 8.3.3.4.2 SPI variant
      4. 8.3.4 Protection and Diagnostics
        1. 8.3.4.1 Over Current Protection (OCP)
        2. 8.3.4.2 Over Temperature Protection (TSD)
        3. 8.3.4.3 Off-State Diagnostics (OLP)
        4. 8.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
        5. 8.3.4.5 VM Over Voltage Monitor
        6. 8.3.4.6 VM Under Voltage Monitor
        7. 8.3.4.7 Power On Reset (POR)
        8. 8.3.4.8 Event Priority
    4. 8.4 Device Functional States
      1. 8.4.1 SLEEP State
      2. 8.4.2 STANDBY State
      3. 8.4.3 Wake-up to STANDBY State
      4. 8.4.4 ACTIVE State
      5. 8.4.5 nSLEEP Reset Pulse (HW Variant Only)
    5. 8.5 Programming - SPI Variant Only
      1. 8.5.1 SPI Interface
      2. 8.5.2 Standard Frame
      3. 8.5.3 SPI Interface for Multiple Peripherals
        1. 8.5.3.1 Daisy Chain Frame for Multiple Peripherals
    6. 8.6 Register Map - SPI Variant Only
      1. 8.6.1 User Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Load Summary
    2. 9.2 Typical Application
      1. 9.2.1 HW Variant
      2. 9.2.2 SPI Variant
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.1 User Registers

The following table lists all the registers that can be accessed by the user. All register addresses NOT listed in this table should be considered as "reserved" locations and access is blocked to this space. Accessing them will cause a SPI_ERR.

Table 8-22 User Registers
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type (2) Addr
DEVICE_ID DEV_ID[5] DEV_ID[4] DEV_ID[3] DEV_ID[2] DEV_ID[1] DEV_ID[0] REV_ID[1] REV_ID[0] R 00h
FAULT_SUMMARY SPI_ERR(3) POR FAULT VMOV VMUV OCP TSD OLA(3) R 01h
STATUS1 OLA1 OLA2 ITRIP_CMP ACTIVE OCP_H1 OCP_L1 OCP_H2 OCP_L2 R 02h
STATUS2 DRVOFF_STAT N/A(4) N/A(4) ACTIVE N/A(4) N/A(4) N/A(4) OLP_CMP R 03h
COMMAND CLR_FLT N/A(4) N/A(4) SPI_IN_LOCK[1] SPI_IN_LOCK[0] (1) N/A(4) REG_LOCK[1] REG_LOCK[0] (1) R/W 08h
SPI_IN N/A(4) N/A(4) N/A(4) N/A(4) S_DRVOFF (1) S_DRVOFF2(1) S_EN_IN1 S_PH_IN2 R/W 09h
CONFIG1 EN_OLA VMOV_SEL[1] VMOV_SEL[0] SSC_DIS(1) OCP_RETRY TSD_RETRY VMOV_RETRY OLA_RETRY R/W 0Ah
CONFIG2 PWM_EXTEND S_DIAG[1] S_DIAG[0] N/A(4) N/A(4) S_ITRIP[2] S_ITRIP[1] S_ITRIP[0] R/W 0Bh
CONFIG3 TOFF[1] TOFF[0] (1) N/A(4) S_SR[2] S_SR[1] S_SR[0] S_MODE[1] S_MODE[0] R/W 0Ch
CONFIG4 TOCP_SEL[1] TOCP_SEL[0] N/A(4) OCP_SEL[1] OCP_SEL[0] DRVOFF_SEL(1) EN_IN1_SEL PH_IN2_SEL R/W 0Dh
(1) Defaulted to 1b on reset, others are defaulted to 0b on reset
(2) R = Read Only, R/W = Read/Write
(3) OLA replaced by SPI_ERR in the first SDO byte response, common to all SPI frames. Refer SDO - Standard frame format.
(4) N/A = Not available (read back of this bit will be 0b)

8.6.1.1 DEVICE_ID register (Address = 00h)

Return to the User Register table.

Device DEVICE_ID value
DRV8243S-Q1 32h
DRV8244S-Q1 42h
DRV8245S-Q1 52h
DRV8243P-Q1 36h
DRV8244P-Q1 46h
DRV8245P-Q1 56h

8.6.1.2 FAULT_SUMMARY Register (Address = 01h) [reset = 40h]

Return to the User Register table.

Bit Field Type Reset Description
7 SPI_ERR R 0b 1b indicates that a SPI communication fault has occurred in the previous SPI frame.
6 POR R 1b 1b indicates that a power-on-reset has been detected.
5 FAULT R 0b Logic OR of SPI_ERR, POR, VMOV, VMUV, OCP, TSD & OLA
4 VMOV R 0b 1b indicates that a VM over voltage has been detected. Refer VMOV_SEL to change thresholds or disable diagnostic, VMOV_RETRY to configure fault reaction.
3 VMUV R 0b 1b indicates that a VM under voltage has been detected.
2 OCP R 0b 1b indicates that an over current has been detected in either one or more power FETs. Refer OCP_SEL, TOCP_SEL to change thresholds & filter times. Refer OCP_RETRY to configure fault reaction.
1 TSD R 0b 1b indicates that an over temperature has been detected. Refer TSD_RETRY to configure fault reaction.
0 OLA R 0b 1b indicates that an open load condition has been detected in the ACTIVE state. Refer to EN_OLA to disable diagnostic, OLA_RETRY to configure fault reaction.

8.6.1.3 STATUS1 Register (Address = 02h) [reset = 00h]

Return to the User Register table.

Bit Field Type Reset Description
7 OLA1 R 0b 1b indicates that an open load condition has been detected in the ACTIVE state on OUT1
6 OLA2 R 0b 1b indicates that an open load condition has been detected in the ACTIVE state on OUT2
5 ITRIP_CMP R 0b 1b indicates that load current has reached the ITRIP regulation level.
4 ACTIVE R 0b 1b indicates that the device is in the ACTIVE state
3 OCP_H1 R 0b 1b indicates that an over current has been detected on the high-side FET (short to GND) on OUT1
2 OCP_L1 R 0b 1b indicates that an over current has been detected on the low-side FET (short to VM) on OUT1
1 OCP_H2 R 0b 1b indicates that an over current has been detected on the high-side FET (short to GND) on OUT2
0 OCP_L2 R 0b 1b indicates that an over current has been detected on the low-side FET (short to VM) on OUT2

8.6.1.4 STATUS2 Register (Address = 03h) [reset = 80h]

Return to the User Register table.

Bit Field Type Reset Description
7 DRVOFF_STAT R 1b

This bit shows the status of the DRVOFF pin. 1b implies the pin status is high.
6, 5 N/A R 0b Not available
4 ACTIVE R 0b 1b indicates that the device is in the ACTIVE state (Copy of bit4 in STATUS1)
3, 2, 1 N/A R 0b Not available
0 OLP_CMP R 0b This bit is the output of the off-state diagnostics (OLP) comparator.

8.6.1.5 COMMAND Register (Address = 08h) [reset = 09h]

Return to the User Register table.

Bit Field Type Reset Description
7 CLR_FLT R/W 0b Clear Fault command - Write 1b to clear all faults reported in the fault registers and de-assert the nFAULT pin
6-5 N/A R 0b Not available
4-3 SPI_IN_LOCK R/W 01b

Write 10b to unlock the SPI_IN register

Write 01b or 00b or 11b to lock the SPI_IN register

SPI_IN register is locked by default.
2 N/A R 0b

Not available
1-0 REG_LOCK R/W 01b

Write 10b to lock the CONFIG registers

Write 01b or 00b or 11b to unlock the CONFIG registers

CONFIG registers are unlocked by default.

8.6.1.6 SPI_IN Register (Address = 09h) [reset = 0Ch]

Return to the User Register table.

Bit Field Type Reset Description
7-4 N/A R 0b Not available
3 S_DRVOFF R/W 1b Register bit equivalent of DRVOFF pin when SPI_IN is unlocked. Refer Register Pin control section. In Independent mode, this bit shuts off half-bridge 1.
2 S_DRVOFF2 R/W 1b Register bit to shut off half-bridge 2 in Independent mode when SPI_IN is unlocked. Refer Register Pin control section
1 S_EN_IN1 R/W 0b Register bit equivalent of EN/IN1 pin when SPI_IN is unlocked. Refer Register Pin control section
0 S_PH_IN2 R/W 0b Register bit equivalent of PH/IN2 pin when SPI_IN is unlocked. Refer Register Pin control section

8.6.1.7 CONFIG1 Register (Address = 0Ah) [reset = 10h]

Return to the User Register table.

Bit Field Type Reset Description
7 EN_OLA R/W 0b Write 1b to enable open load detection in the active state. In Independent mode, OLA is always disabled for low-side load. Refer DIAG section.
6-5 VMOV_SEL R/W 0b Determines the thresholds for the VM over voltage diagnostics

00b = VM > 35 V

01b = VM > 28 V

10b = VM > 18 V

11b = VMOV disabled
4 SSC_DIS R/W 1b 0b: Enables the spread spectrum clocking feature
3 OCP_RETRY R/W 0b Write 1b to configure fault reaction to retry setting on the detection of over current, else the fault reaction is latched
2 TSD_RETRY R/W 0b Write 1b to configure fault reaction to retry setting on the detection of over temperature, else the fault reaction is latched
1 VMOV_RETRY R/W 0b Write 1b to configure fault reaction to retry setting on the detection of VMOV, else the fault reaction is latched.
Note: For the SPI (P) variant, this bit also controls the fault reaction for a VM under voltage detection.
0 OLA_RETRY R/W 0b Write 1b to configure fault reaction to retry setting on the detection of open load during active, else the fault reaction is latched.

8.6.1.8 CONFIG2 Register (Address = 0Bh) [reset = 00h]

Return to the User Register table.

Bit Field Type Reset Description
7 PWM_EXTEND R/W 0b Write 1b to access additional Hi-Z (coast) states in the PWM mode - refer PWM EXTEND table
6-5 S_DIAG R/W 0b Load type indication - refer to DIAG table
4-3 N/A R 0b Not available
2-0 S_ITRIP R/W 0b ITRIP level configuration - refer ITRIP table

8.6.1.9 CONFIG3 Register (Address = 0Ch) [reset = 40h]

Return to the User Register table.

Bit Field Type Reset Description
7-6 TOFF R/W 1b TOFF time used for ITRIP current regulation

00b = 20 µsec

01b = 30 µsec

10b = 40 µsec

11b = 50 µsec
5 N/A R 0b Not available
4-2 S_SR R/W 0b Slew Rate configuration - refer to Section 8.3.3.1
1-0 S_MODE R/W 0b Device mode configuration - refer MODE table

8.6.1.10 CONFIG4 Register (Address = 0Dh) [reset = 04h]

Return to the User Register table.

Bit Field Type Reset Description
7-6 TOCP_SEL R/W 0b Filter time for over current detection configuration

00b = 6 µsec

01b = 3 µsec

10b = 1.5 µsec

11b = Minimum (~0.2 µsec)
5 N/A R 0b Not available
4-3 OCP_SEL R/W 0b Threshold for over current detection configuration

00b = 100% setting

01b, 11b = 50% setting

10b = 75% setting

2 DRVOFF_SEL R/W 1b DRVOFF pin - register logic combination, when SPI_IN is unlocked

0b = OR

1b = AND
1 EN_IN1_SEL R/W 0b EN/IN1 pin - register logic combination, when SPI_IN is unlocked

0b = OR

1b = AND
0 PH_IN2_SEL R/W 0b PH/IN2 pin - register logic combination, when SPI_IN is unlocked

0b = OR

1b = AND