SLVSG23C December 2021 – August 2022 DRV8243-Q1
PRODUCTION DATA
The following table lists all the registers that can be accessed by the user. All register addresses NOT listed in this table should be considered as "reserved" locations and access is blocked to this space. Accessing them will cause a SPI_ERR.
Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | Type (2) | Addr |
---|---|---|---|---|---|---|---|---|---|---|
DEVICE_ID | DEV_ID[5] | DEV_ID[4] | DEV_ID[3] | DEV_ID[2] | DEV_ID[1] | DEV_ID[0] | REV_ID[1] | REV_ID[0] | R | 00h |
FAULT_SUMMARY | SPI_ERR(3) | POR | FAULT | VMOV | VMUV | OCP | TSD | OLA(3) | R | 01h |
STATUS1 | OLA1 | OLA2 | ITRIP_CMP | ACTIVE | OCP_H1 | OCP_L1 | OCP_H2 | OCP_L2 | R | 02h |
STATUS2 | DRVOFF_STAT | N/A(4) | N/A(4) | ACTIVE | N/A(4) | N/A(4) | N/A(4) | OLP_CMP | R | 03h |
COMMAND | CLR_FLT | N/A(4) | N/A(4) | SPI_IN_LOCK[1] | SPI_IN_LOCK[0] (1) | N/A(4) | REG_LOCK[1] | REG_LOCK[0] (1) | R/W | 08h |
SPI_IN | N/A(4) | N/A(4) | N/A(4) | N/A(4) | S_DRVOFF (1) | S_DRVOFF2(1) | S_EN_IN1 | S_PH_IN2 | R/W | 09h |
CONFIG1 | EN_OLA | VMOV_SEL[1] | VMOV_SEL[0] | SSC_DIS(1) | OCP_RETRY | TSD_RETRY | VMOV_RETRY | OLA_RETRY | R/W | 0Ah |
CONFIG2 | PWM_EXTEND | S_DIAG[1] | S_DIAG[0] | N/A(4) | N/A(4) | S_ITRIP[2] | S_ITRIP[1] | S_ITRIP[0] | R/W | 0Bh |
CONFIG3 | TOFF[1] | TOFF[0] (1) | N/A(4) | S_SR[2] | S_SR[1] | S_SR[0] | S_MODE[1] | S_MODE[0] | R/W | 0Ch |
CONFIG4 | TOCP_SEL[1] | TOCP_SEL[0] | N/A(4) | OCP_SEL[1] | OCP_SEL[0] | DRVOFF_SEL(1) | EN_IN1_SEL | PH_IN2_SEL | R/W | 0Dh |
Return to the User Register table.
Device | DEVICE_ID value |
---|---|
DRV8243S-Q1 | 32h |
DRV8244S-Q1 | 42h |
DRV8245S-Q1 | 52h |
DRV8243P-Q1 | 36h |
DRV8244P-Q1 | 46h |
DRV8245P-Q1 | 56h |
Return to the User Register table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SPI_ERR | R | 0b | 1b indicates that a SPI communication fault has occurred in the previous SPI frame. |
6 | POR | R | 1b | 1b indicates that a power-on-reset has been detected. |
5 | FAULT | R | 0b | Logic OR of SPI_ERR, POR, VMOV, VMUV, OCP, TSD & OLA |
4 | VMOV | R | 0b | 1b indicates that a VM over voltage has been detected. Refer VMOV_SEL to change thresholds or disable diagnostic, VMOV_RETRY to configure fault reaction. |
3 | VMUV | R | 0b | 1b indicates that a VM under voltage has been detected. |
2 | OCP | R | 0b | 1b indicates that an over current has been detected in either one or more power FETs. Refer OCP_SEL, TOCP_SEL to change thresholds & filter times. Refer OCP_RETRY to configure fault reaction. |
1 | TSD | R | 0b | 1b indicates that an over temperature has been detected. Refer TSD_RETRY to configure fault reaction. |
0 | OLA | R | 0b | 1b indicates that an open load condition has been detected in the ACTIVE state. Refer to EN_OLA to disable diagnostic, OLA_RETRY to configure fault reaction. |
Return to the User Register table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | OLA1 | R | 0b | 1b indicates that an open load condition has been detected in the ACTIVE state on OUT1 |
6 | OLA2 | R | 0b | 1b indicates that an open load condition has been detected in the ACTIVE state on OUT2 |
5 | ITRIP_CMP | R | 0b | 1b indicates that load current has reached the ITRIP regulation level. |
4 | ACTIVE | R | 0b | 1b indicates that the device is in the ACTIVE state |
3 | OCP_H1 | R | 0b | 1b indicates that an over current has been detected on the high-side FET (short to GND) on OUT1 |
2 | OCP_L1 | R | 0b | 1b indicates that an over current has been detected on the low-side FET (short to VM) on OUT1 |
1 | OCP_H2 | R | 0b | 1b indicates that an over current has been detected on the high-side FET (short to GND) on OUT2 |
0 | OCP_L2 | R | 0b | 1b indicates that an over current has been detected on the low-side FET (short to VM) on OUT2 |
Return to the User Register table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DRVOFF_STAT | R | 1b |
This bit shows the status of the DRVOFF pin. 1b implies the pin status is high. |
6, 5 | N/A | R | 0b | Not available |
4 | ACTIVE | R | 0b | 1b indicates that the device is in the ACTIVE state (Copy of bit4 in STATUS1) |
3, 2, 1 | N/A | R | 0b | Not available |
0 | OLP_CMP | R | 0b | This bit is the output of the off-state diagnostics (OLP) comparator. |
Return to the User Register table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CLR_FLT | R/W | 0b | Clear Fault command - Write 1b to clear all faults reported in the fault registers and de-assert the nFAULT pin |
6-5 | N/A | R | 0b | Not available |
4-3 | SPI_IN_LOCK | R/W | 01b |
Write 10b to unlock the SPI_IN register Write 01b or 00b or 11b to lock the SPI_IN register SPI_IN register is locked by default. |
2 | N/A | R | 0b |
Not available |
1-0 | REG_LOCK | R/W | 01b |
Write 10b to lock the CONFIG registers Write 01b or 00b or 11b to unlock the CONFIG registers CONFIG registers are unlocked by default. |
Return to the User Register table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | N/A | R | 0b | Not available |
3 | S_DRVOFF | R/W | 1b | Register bit equivalent of DRVOFF pin when SPI_IN is unlocked. Refer Register Pin control section. In Independent mode, this bit shuts off half-bridge 1. |
2 | S_DRVOFF2 | R/W | 1b | Register bit to shut off half-bridge 2 in Independent mode when SPI_IN is unlocked. Refer Register Pin control section |
1 | S_EN_IN1 | R/W | 0b | Register bit equivalent of EN/IN1 pin when SPI_IN is unlocked. Refer Register Pin control section |
0 | S_PH_IN2 | R/W | 0b | Register bit equivalent of PH/IN2 pin when SPI_IN is unlocked. Refer Register Pin control section |
Return to the User Register table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EN_OLA | R/W | 0b | Write 1b to enable open load detection in the active state. In Independent mode, OLA is always disabled for low-side load. Refer DIAG section. |
6-5 | VMOV_SEL | R/W | 0b | Determines the
thresholds for the VM over voltage diagnostics 00b = VM > 35 V 01b = VM > 28 V 10b = VM > 18 V 11b = VMOV disabled |
4 | SSC_DIS | R/W | 1b | 0b: Enables the spread spectrum clocking feature |
3 | OCP_RETRY | R/W | 0b | Write 1b to configure fault reaction to retry setting on the detection of over current, else the fault reaction is latched |
2 | TSD_RETRY | R/W | 0b | Write 1b to configure fault reaction to retry setting on the detection of over temperature, else the fault reaction is latched |
1 | VMOV_RETRY | R/W | 0b | Write 1b to
configure fault reaction to retry setting on the detection of VMOV,
else the fault reaction is latched. Note: For the SPI (P)
variant, this bit also controls the fault reaction for a VM
under voltage detection. |
0 | OLA_RETRY | R/W | 0b | Write 1b to configure fault reaction to retry setting on the detection of open load during active, else the fault reaction is latched. |
Return to the User Register table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PWM_EXTEND | R/W | 0b | Write 1b to access additional Hi-Z (coast) states in the PWM mode - refer PWM EXTEND table |
6-5 | S_DIAG | R/W | 0b | Load type indication - refer to DIAG table |
4-3 | N/A | R | 0b | Not available |
2-0 | S_ITRIP | R/W | 0b | ITRIP level configuration - refer ITRIP table |
Return to the User Register table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | TOFF | R/W | 1b | TOFF time used
for ITRIP current regulation 00b = 20 µsec 01b = 30 µsec 10b = 40 µsec 11b = 50 µsec |
5 | N/A | R | 0b | Not available |
4-2 | S_SR | R/W | 0b | Slew Rate configuration - refer to Section 8.3.3.1 |
1-0 | S_MODE | R/W | 0b | Device mode configuration - refer MODE table |
Return to the User Register table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | TOCP_SEL | R/W | 0b | Filter time
for over current detection configuration 00b = 6 µsec 01b = 3 µsec 10b = 1.5 µsec 11b = Minimum (~0.2 µsec) |
5 | N/A | R | 0b | Not available |
4-3 | OCP_SEL | R/W | 0b | Threshold for
over current detection configuration 00b = 100% setting 01b, 11b = 50% setting 10b = 75% setting |
2 | DRVOFF_SEL | R/W | 1b | DRVOFF pin - register logic combination, when
SPI_IN is unlocked 0b = OR 1b = AND |
1 | EN_IN1_SEL | R/W | 0b | EN/IN1 pin - register logic combination, when
SPI_IN is unlocked 0b = OR 1b = AND |
0 | PH_IN2_SEL | R/W | 0b | PH/IN2 pin - register logic combination, when
SPI_IN is unlocked 0b = OR 1b = AND |