SLOS846C September   2013  – December 2016 DRV8303

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Current Shunt Amplifier Characteristics
    7. 6.7 SPI Characteristics (Slave Mode Only)
    8. 6.8 Gate Timing and Protection Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three-Phase Gate Driver
      2. 7.3.2 Current Shunt Amplifiers
      3. 7.3.3 Protection Features
        1. 7.3.3.1 Power Stage Protection
        2. 7.3.3.2 Overcurrent Protection (OCP) and Reporting
        3. 7.3.3.3 Undervoltage Protection (UVLO)
        4. 7.3.3.4 Overvoltage Protection (GVDD_OV)
        5. 7.3.3.5 Overtemperature Protection
        6. 7.3.3.6 Fault and Protection Handling
      4. 7.3.4 Start-Up and Shutdown Sequence Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 EN_GATE
      2. 7.4.2 DTC
      3. 7.4.3 VDD_SPI
      4. 7.4.4 DC_CAL
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 SPI
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
      1. 7.6.1 Read / Write Bit
      2. 7.6.2 Address Bits
      3. 7.6.3 SPI Data Bits
        1. 7.6.3.1 Status Registers
        2. 7.6.3.2 Control Registers
        3. 7.6.3.3 Overcurrent Adjustment
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Gate Driver Power-Up Sequencing Errata
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Drive Average Current Load
        2. 8.2.2.2 Overcurrent Protection Setup
        3. 8.2.2.3 Sense Amplifier Setup
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from B Revision (November 2015) to C Revision

  • Added the maximum voltage difference and maximum voltage parameters for the BST_X, GH_X, SL_X, and SH_X pins in the Absolute Maximum Ratings tableGo
  • Added the Documentation support and Receiving Notification of Documentation Updates sections Go

Changes from A Revision (October 2013) to B Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Updated titleGo
  • VPVDD absolute max voltage rating reduced from 70 V to 65 V Go
  • Clarification made on how the OCP status bits report in Overcurrent Protection (OCP) and Reporting Go
  • Update to PVDD undervoltage protection in Undervoltage Protection (UVLO) describing specific transient brownout issue.Go
  • Update to EN_GATE pin functional description in EN_GATE clarifying proper EN_GATE reset pulse lengths. Go
  • Added gate driver power-up sequencing errata Go