SLES256F May   2010  – May 2022 DRV8312 , DRV8332

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Dissipation Ratings
    6. 6.6 Power Deratings (DRV8312)
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Error Reporting
      2. 7.3.2 Device Protection System
        1. 7.3.2.1 Bootstrap Capacitor Undervoltage Protection
          1. 7.3.2.1.1 Overcurrent (OC) Protection
        2. 7.3.2.2 Overtemperature Protection
        3. 7.3.2.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
        4. 7.3.2.4 Device Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 Different Operational Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Three-Phase Operation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Motor Voltage
          2. 8.2.1.2.2 Current Requirement of 12 V Power Supply
          3. 8.2.1.2.3 Voltage of Decoupling Capacitor
          4. 8.2.1.2.4 Overcurrent Threshold
          5. 8.2.1.2.5 Sense Resistor
          6. 8.2.1.2.6 Output Inductor Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DRV8312 Application Diagram for Three-Phase Operation
      3. 8.2.3 Control Signal Logic With Conventional 6 PWM Input Scheme
      4. 8.2.4 Hall Sensor Control With 6 Steps Trapezoidal Scheme
      5. 8.2.5 Sensorless Control With 6 Steps Trapezoidal Scheme
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
    2. 9.2 System Power-Up and Power-Down Sequence
      1. 9.2.1 Powering Up
      2. 9.2.2 Powering Down
    3. 9.3 System Design Recommendations
      1. 9.3.1 VREG Pin
      2. 9.3.2 VDD Pin
      3. 9.3.3 OTW Pin
      4. 9.3.4 FAULT Pin
      5. 9.3.5 OC_ADJ Pin
      6. 9.3.6 PWM_X and RESET_X Pins
      7. 9.3.7 Mode Select Pins
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Material Recommendation
      2. 10.1.2 Ground Plane
      3. 10.1.3 Decoupling Capacitor
      4. 10.1.4 AGND
    2. 10.2 Layout Example
      1. 10.2.1 Current Shunt Resistor
        1. 10.2.1.1 66
    3. 10.3 Thermal Considerations
      1. 10.3.1 Thermal Via Design Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-A2A6BBEE-6870-4DDC-A9B1-3BAD2A750C90-low.gif
DRV8312: 44-pin TSSOP power pad down DDW package. This package contains a thermal pad that is located on the bottom side of the device for dissipating heat through PCB.
Figure 5-1 DV8312HTSSOP (DDW)(Top View)
GUID-4738B006-299E-4DC0-B5A4-365A1F539E30-low.gif
DRV8332: 36-pin PSOP3 DKD package. This package contains a thick heat slug that is located on the top side of the device for dissipating heat through heatsink.
Figure 5-2 DRV8332HSSOP (DKD)(Top View)
Table 5-1 Pin Functions
PIN I/O TYPE (1) DESCRIPTION
NAME DRV8312 DRV8332
AGND 12 9 P Analog ground
BST_A 24 35 P High side bootstrap supply (BST), external capacitor to OUT_A required
BST_B 33 28 P High side bootstrap supply (BST), external capacitor to OUT_B required
BST_C 43 20 P High side bootstrap supply (BST), external capacitor to OUT_C required
GND 13, 36, 37 8 P Ground
GND_A 29 32 P Power ground for half-bridge A
GND_B 30 31 P Power ground for half-bridge B
GND_C 38 23 P Power ground for half-bridge C
GVDD_A 23 36 P Gate-drive voltage supply
GVDD_B 22 1 P Gate-drive voltage supply
GVDD_C 1, 44 18, 19 P Gate-drive voltage supply
M1 8 13 I Mode selection pin
M2 9 12 I Reserved mode selection pin. AGND connection is recommended
M3 10 11 I Reserved mode selection pin, VREG connection is recommended
NC 3, 4, 19, 20, 25, 34, 35, 42 26, 27 - No connection pin. Ground connection is recommended
OC_ADJ 14 7 O Analog overcurrent programming pin, requires resistor to AGND
OTW 21 2 O Overtemperature warning signal, open-drain, active-low. An internal pullup resistor to VREG (3.3 V) is provided on output. Level compliance for 5-V logic can be obtained by adding external pullup resistor to 5 V
OUT_A 28 33 O Output, half-bridge A
OUT_B 31 30 O Output, half-bridge B
OUT_C 39 22 O Output, half-bridge C
PVDD_A 26, 27 34 P Power supply input for half-bridge A requires close decoupling capacitor to ground.
PVDD_B 32 29 P Power supply input for half-bridge B requires close decoupling capacitor to gound.
PVDD_C 40, 41 21 P Power supply input for half-bridge C requires close decoupling capacitor to ground.
PWM_A 17 4 I Input signal for half-bridge A
PWM_B 15 6 I Input signal for half-bridge B
PWM_C 5 16 I Input signal for half-bridge C
RESET_A 16 5 I Reset signal for half-bridge A, active-low
RESET_B 7 14 I Reset signal for half-bridge B, active-low
RESET_C 6 15 I Reset signal for half-bridge C, active-low
FAULT 18 3 O Fault signal, open-drain, active-low. An internal pullup resistor to VREG (3.3 V) is provided on output. Level compliance for 5-V logic can be obtained by adding external pullup resistor to 5 V
VDD 2 17 P Power supply for digital voltage regulator requires capacitor to ground for decoupling.
VREG 11 10 P Digital regulator supply filter pin requires 0.1-μF capacitor to AGND.
THERMAL PAD -- N/A T Solder the exposed thermal pad at the bottom of the DRV8312DDW package to the landing pad on the PCB. Connect the landing pad through vias to large ground plate for better thermal dissipation.
HEAT SLUG N/A -- T Mount heatsink with thermal interface to the heat slug on the top of the DRV8332DKD package to improve thermal dissipation.
(1) I = input, O = output, P = power, T = thermal
Mode Selection Pins
MODE PINS DESCRIPTION
M3 M2 M1
1 0 0 Three-phase or three half bridges with cycle-by-cycle current limit
1 0 1 Three-phase or three half bridges with OC latching shutdown (no cycle-by-cycle current limit)
0 x x Reserved