The DRV8313 provides three individually controllable half-H-bridge drivers. The device is intended to drive a three-phase brushless-DC motor, although it can also be used to drive solenoids or other loads. Each output driver channel consists of N-channel power MOSFETs configured in a 1/2-H-bridge configuration. Each 1/2-H-bridge driver has a dedicated ground terminal, which allows independent external current sensing.
An uncommitted comparator is integrated into the DRV8313, which allows for the construction of current-limit circuitry or other functions.
Internal protection functions are provided for undervoltage, charge pump faults, overcurrent, short circuits, and overtemperature. Fault conditions are indicated by the nFAULT pin.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DRV8313 | HTSSOP (28) | 9.70 mm × 4.40 mm |
VQFN (36) | 6.00 mm × 6.00 mm |
Changes from C Revision (November 2015) to D Revision
Changes from B Revision (January 2015) to C Revision
Changes from A Revision (November 2012) to B Revision
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
PWP | RHH | |||
COMPN | 13 | 22 | I | Comparator negative input. Uncommitted comparator input |
COMPP | 12 | 21 | I | Comparator positive input. Uncommitted comparator input |
CPL | 1 | 5 | PWR | Charge pump. Connect a VM-rated, 0.01-µF ceramic capacitor between CPH and CPL. |
CPH | 2 | 6 | PWR | Charge pump. Connect a VM-rated, 0.01-µF ceramic capacitor between CPH and CPL. |
EN1 | 26 | 1 | I | Channel enable. Logic high enables the 1/2-H bridge channel; internal pulldown |
EN2 | 24 | 35 | I | Channel enable. Logic high enables the 1/2-H bridge channel; internal pulldown |
EN3 | 22 | 33 | I | Channel enable. Logic high enables the 1/2-H bridge channel; internal pulldown |
GND | 14, 20, 28 | 3, 17, 20, 23, 24, 30, 31, 32, | PWR | Device ground. Connect to system ground |
IN1 | 27 | 2 | I | Channel input. Logic high pulls 1/2-H bridge high, logic low pulls 1/2-H bridge low; no effect when ENx is low; internal pulldown input. |
IN2 | 25 | 36 | I | Channel input. Logic high pulls 1/2-H bridge high, logic low pulls 1/2-H bridge low; no effect when ENx is low; internal pulldown input. |
IN3 | 23 | 34 | I | Channel input. Logic high pulls 1/2-H bridge high, logic low pulls 1/2-H bridge low; no effect when ENx is low; internal pulldown input. |
NC | 21 | 4, 8, 14 | NC | No internal connection. Recommended net given in block diagram (if any) |
nCOMPO | 19 | 29 | OD | Comparator output. Uncommitted comparator output; open drain requires an external pullup. |
nFAULT | 18 | 28 | OD | Fault indication pin. Pulled logic-low with fault condition; open-drain output requires an external pullup. |
nRESET | 16 | 26 | I | Reset input. Active-low reset input initializes internal logic, clears faults, and disables the outputs, internal pulldown |
nSLEEP | 17 | 27 | I | Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown |
OUT1 | 5 | 10 | O | Half-H bridge output, connect to the load |
OUT2 | 8 | 13 | O | Half-H bridge output, connect to the load |
OUT3 | 9 | 15 | O | Half-H bridge output, connect to the load |
PGND1 | 6 | 11 | PWR | Low-side FET source. Connect to GND or to low-side current-sense resistors |
PGND2 | 7 | 12 | PWR | Low-side FET source. Connect to GND or to low-side current-sense resistors |
PGND3 | 10 | 16 | PWR | Low-side FET source. Connect to GND or to low-side current-sense resistors |
RSVD | — | 18 | — | Reserved. Leave this pin disconnected. |
V3P3 | 15 | 25 | PWR | Internal regulator. Internal supply voltage; bypass to GND with a 6.3-V, 0.47-µF ceramic capacitor; up to 10-mA external load |
VCP | 3 | 7 | PWR | Charge pump. Connect a 16-V, 0.1-µF ceramic capacitor to VM |
VM | 4, 11 | 9, 19 | PWR | Power supply. Connect to motor supply voltage; bypass to GND with two 0.1-µF capacitors (for each pin) plus one bulk capacitor rated for VM |
Thermal pad | PWR | Must be connected to ground |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±3000 | V | |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VM | Motor power-supply voltage(1) | 8 | 60 | V |
VIN | Digital pin voltage | 0 | 5.5 | V |
fPWM | Applied PWM signal on ENx, INx | 0 | 250 | kHz |
VGNDX | PGNDx pin voltage | –500 | 500 | mV |
IV3P3 | V3P3 load current | 0 | 10(2) | mA |
TA | Operating ambient temperature | –40 | 125 | °C |
THERMAL METRIC (1) | DRV8313 | UNIT | ||
---|---|---|---|---|
PWP (HTSSOP) | RHH (VQFN) | |||
28 PINS | 36 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 31.6 | 31.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 15.9 | 17.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 5.6 | 5.6 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 5.5 | 5.6 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.4 | 1.3 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLIES | ||||||
IVM | VM operating supply current | VM = 24 V, fPWM < 50 kHz | 1 | 5 | mA | |
IVMQ | VM sleep-mode supply current | VM = 24 V | 500 | 800 | µA | |
INTERNAL REGULATOR (V3P3) | ||||||
V3P3 | V3P3 voltage | IOUT = 0 to 10 mA | 3.1 | 3.3 | 3.52 | V |
LOGIC-LEVEL INPUTS (nSLEEP, ENx, INx) | ||||||
VIL | Input low voltage | 0.6 | 0.7 | V | ||
VIH | Input high voltage | 2.2 | 5.25 | V | ||
VHYS | Input hysteresis | 50 | 600 | mV | ||
IIL | Input low current | VIN = 0 | –5 | 5 | µA | |
IIH | Input high current | VIN = 3.3 V | 100 | µA | ||
RPD | Pulldown resistance | 100 | kΩ | |||
OPEN-DRAIN OUTPUTS (nFAULT and nCOMPO) | ||||||
VOL | Output low voltage | IO = 5 mA | 0.5 | V | ||
IOH | Output high leakage current | VO = 3.3 V | 1 | µA | ||
COMPARATOR (COMPP, COMPN, nCOMPO) | ||||||
VCM | Common-mode input-voltage range | 0 | 5 | V | ||
VIO | Input offset voltage | –7 | 7 | mV | ||
IIB | Input bias current | –300 | 300 | nA | ||
tR | Response time | 100-mV step with 10-mV overdrive | 2 | µs | ||
H-BRIDGE FETs | ||||||
rDS(on) | High-side FET ON-resistance | VM = 24 V, IO = 1 A, TJ = 25°C | 0.24 | Ω | ||
VM = 24 V, IO = 1 A, TJ = 85°C(1) | 0.29 | 0.39 | ||||
Low-side FET ON-resistance | VM = 24 V, IO = 1 A, TJ = 25°C | 0.24 | Ω | |||
VM = 24 V, IO = 1 A, TJ = 85°C(1) | 0.29 | 0.39 | ||||
IOFF | Off-state leakage current | –2 | 2 | µA | ||
PROTECTION CIRCUITS | ||||||
VUVLO | VM undervoltage lockout voltage | VM rising | 6.3 | 8 | V | |
IOCP | Overcurrent protection trip level | 3 | 5 | A | ||
tOCP | Overcurrent protection deglitch time | 5 | µs | |||
TTSD(1) | Thermal shutdown temperature | Die temperature | 150 | 160 | 180 | °C |
THYS(1) | Thermal shutdown hysteresis | Die temperature | 35 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
t1 | Delay time, ENx high to OUTx high | INx = 1 | 130 | 330 | ns | |
t2 | Delay time, ENx low to OUTx low | INx = 1 | 275 | 475 | ns | |
t3 | Delay time, ENx high to OUTx low | INx = 0 | 100 | 300 | ns | |
t4 | Delay time, ENx low to OUTx high | INx = 0 | 200 | 400 | ns | |
t5 | Delay time, INx high to OUTx high | ENx = 1 | 300 | 500 | ns | |
t6 | Delay time, INx low to OUTx low | ENx = 1 | 275 | 475 | ns | |
tr | Output rise time, resistive load to GND | 30 | 150 | ns | ||
tf | Output fall time, resistive load to GND | 30 | 150 | ns | ||
tDEAD(1) | Output dead time | 90 | ns |
The DRV8313 integrates three independent 2.5-A half-H bridges, protection circuits, sleep mode, fault reporting, and a comparator. The single power supply supports a wide 8-V to 60-V range, making it well-suited for motor drive applications.
The DRV8313 contains three half-H-bridge drivers. The source terminals of the low-side FETs of all three half-H-bridges terminate at separate pins (PGND1, PGND2, and PGND3) to allow the use of a low-side current-sense resistor on each output, if desired. The user can also connect all three together to a single low-side sense resistor, or can connect them directly to ground if current sensing is unneeded.
If using a low-side sense resistor, ensure that the voltage on the PGND1, PGND2, or PGND3 pin does not exceed ±500 mV.
The device has two VM motor power-supply pins. Connect both VM pins together to the motor-supply voltage.
The INx input pins directly control the state (high or low) of the OUTx outputs; the ENx input pins enable or disable the OUTx driver. Table 1 shows the logic:
INx | ENx | OUTx |
---|---|---|
X | 0 | Z |
0 | 1 | L |
1 | 1 | H |
Because the output stages use N-channel FETs, the device requires a gate-drive voltage higher than the VM power supply to enhance the high-side FETs fully. The DRV8313 integrates a charge-pump circuit that generates a voltage above the VM supply for this purpose.
The charge pump requires two external capacitors for operation. See the block diagram and pin descriptions for details on these capacitors (value, connection, and so forth).
The charge pump shuts down when nSLEEP is low.
The DRV8313 includes an uncommitted comparator, which can find use as a current-limit comparator or for other purposes.
Figure 12 shows connections to use the comparator to sense current for implementing a current limit. Current from all three low-side FETs is sensed using a single low-side sense resistor. The voltage across the sense resistor is compared with a reference, and when the sensed voltage exceeds the reference, a current-limit condition is signaled to the controller. The V3P3 internal voltage regulator can be used to set the reference voltage of the comparator.
The DRV8313 has full protection against undervoltage, overcurrent, and overtemperature events.
If at any time the voltage on the VM pin falls below the undervoltage threshold voltage (VUVLO), all FETs in the H-bridge will be disabled, the charge pump will be disabled, the internal logic is reset, and the nFAULT pin will be driven low. Operation will resume when VM rises above the UVLO threshold. The nFAULT pin will be released after operation has resumed.
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level operation will automatically resume. The nFAULT pin will be released after operation has resumed.
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than tOCP, the device disables the channel experiencing the overcurrent and drives the nFAULT pin low. The driver remains off until either assertion of nRESET or the cycling of VM power.
Overcurrent conditions on both high- and low-side devices, that is, a short to ground, supply, or across the motor winding, all result in an overcurrent shutdown.
FAULT | CONDITION | ERROR REPORT | H-BRIDGE | CHARGE PUMP | V3P3 | RECOVERY |
---|---|---|---|---|---|---|
VM undervoltage (UVLO) |
VM < VUVLO
(max 8 V) |
nFAULT | Disabled | Disabled |
Operating |
VM > VUVLO
(max 8 V) |
Thermal Shutdown (TSD) |
TJ > TTSD
(min 150°C) |
nFAULT | Disabled | Operating |
Operating |
TJ < TTSD - THYS
(THYS typ 35°C) |
Overcurrent (OCP) |
IOUT > IOCP
(min 3 A) |
nFAULT | Disabled | Operating |
Operating |
nRESET |
The DRV8313 is active unless the nSLEEP pin is brought logic low. In sleep mode the charge pump is disabled, the output FETs are disabled Hi-Z, and the V3P3 regulator is disabled. The DRV313 is brought out of sleep mode automatically if nSLEEP is brought logic high.
The nRESET pin, when driven low, resets any faults. It also disables the output drivers while it is active. The device ignores all inputs while nRESET is active. Note that there is an internal power-up-reset circuit, so that driving nRESET at power up is not required.
Driving nSLEEP low puts the device into a low-power sleep state. Entering this state disables the output drivers, stops the gate-drive charge pump, resets all internal logic (including faults), and stops all internal clocks. In this state, the device ignores all inputs until nSLEEP returns inactive-high. When returning from sleep mode, some time (approximately 1 ms) must pass before the motor driver becomes fully operational. The V3P3 regulator remains operational in sleep mode.
FAULT | CONDITION | H-BRIDGE | CHARGE PUMP | V3P3 |
---|---|---|---|---|
Operating | 8 V < VM < 60 V nSLEEP pin = 1 |
Operating | Operating | Operating |
Sleep mode | 8 V < VM < 60 V nSLEEP pin = 0 |
Disabled | Disabled | Disabled |
Fault encountered | VM undervoltage (UVLO) | Disabled | Disabled | Operating |
Overcurrent (OCP) | Disabled | Operating | Operating | |
Thermal shutdown (TSD) | Disabled | Operating | Operating |