SLVSHB1A March   2023  – November 2024 DRV8329-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 2pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three BLDC Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 6x PWM Mode
          2. 7.3.1.1.2 3x PWM Mode
        2. 7.3.1.2 Device Hardware Interface
        3. 7.3.1.3 Gate Drive Architecture
          1. 7.3.1.3.1 Propagation Delay
          2. 7.3.1.3.2 Deadtime and Cross-Conduction Prevention
      2. 7.3.2 AVDD Linear Voltage Regulator
      3. 7.3.3 Pin Diagrams
      4. 7.3.4 Low-Side Current Sense Amplifiers
        1. 7.3.4.1 Current Sense Operation
      5. 7.3.5 Gate Driver Shutdown Sequence (DRVOFF)
      6. 7.3.6 Gate Driver Protective Circuits
        1. 7.3.6.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.6.2 AVDD Power on Reset (AVDD_POR)
        3. 7.3.6.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.6.4 BST Undervoltage Lockout (BST_UV)
        5. 7.3.6.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.6.6 VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.6.7 Thermal Shutdown (OTSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Gate Driver Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
        3. 7.4.1.3 Fault Reset (nSLEEP Reset Pulse)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Three Phase Brushless-DC Motor Control
        1. 8.2.1.1 Detailed Design Procedure
          1. 8.2.1.1.1  Motor Voltage
          2. 8.2.1.1.2  Bootstrap Capacitor and GVDD Capacitor Selection
          3. 8.2.1.1.3  Gate Drive Current
          4. 8.2.1.1.4  Gate Resistor Selection
          5. 8.2.1.1.5  System Considerations in High Power Designs
            1. 8.2.1.1.5.1 Capacitor Voltage Ratings
            2. 8.2.1.1.5.2 External Power Stage Components
            3. 8.2.1.1.5.3 Parallel MOSFET Configuration
          6. 8.2.1.1.6  Dead Time Resistor Selection
          7. 8.2.1.1.7  VDSLVL Selection
          8. 8.2.1.1.8  AVDD Power Losses
          9. 8.2.1.1.9  Current Sensing and Output Filtering
          10. 8.2.1.1.10 Power Dissipation and Junction Temperature Losses
      2. 8.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance Sizing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Thermal Considerations
        1. 8.4.2.1 Power Dissipation
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Related Links
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Community Resources
    6. 9.6 Trademarks
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.2.1.1.2 Bootstrap Capacitor and GVDD Capacitor Selection

The bootstrap capacitor must be sized to maintain the bootstrap voltage above the undervoltage lockout for normal operation. Equation 4 calculates the maximum allowable voltage drop across the bootstrap capacitor:

Equation 4. DRV8329-Q1

=12 V – 0.85 V – 4.45 V = 6.7 V

where

  • VGVDD is the supply voltage of the gate drive
  • VBOOTD is the forward voltage drop of the bootstrap diode
  • VBSTUV is the threshold of the bootstrap undervoltage lockout

In this example the allowed voltage drop across bootstrap capacitor is 6.7 V. It is generally recommended that ripple voltage on both the bootstrap capacitor and GVDD capacitor should be minimized as much as possible. Many of commercial, industrial, and automotive applications use ripple value between 0.5 V to 1 V.

The total charge needed per switching cycle can be estimated with Equation 5:

Equation 5. QTOT=QG+ILBS_TRANfSW

=54 nC + 115 μA/20 kHz = 54 nC + 5.8 nC = 59.8nC

where

  • QG is the total MOSFET gate charge
  • ILBS_TRAN is the bootstrap pin leakage current
  • fSW is the is the PWM frequency

The minimum bootstrap capacitor can then be estimated as below assuming 1V of ΔVBSTx:

Equation 6. DRV8329-Q1

= 59.8 nC / 1 V = 59.8 nF

The calculated value of minimum bootstrap capacitor is 59.8 nF. It should be noted that, this value of capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than calculated value to allow for situations where the power stage may skip pulse due to various transient conditions. It is recommended to use a 100 nF bootstrap capacitor in this example. It is also recommenced to include enough margin and place the bootstrap capacitor as close to the BSTx and SHx pins as possible.

Equation 7. DRV8329-Q1

= 10*100 nF= 1 μF

For this example application, choose a 1-µF CGVDD capacitor. Choose a capacitor with a voltage rating at least twice the maximum voltage that it will be exposed to because most ceramic capacitors lose significant capacitance when biased. This value also improves the long-term reliability of the system.

Note: For higher power system requiring 100% duty cycle support for longer duration it is recommended to use CBSTx of ≥1μF and CGVDD of ≥10 μF.